Semiconductor-element-including memory device
View Patent ↗A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.
1. A semiconductor-element-including memory device that is a memory device in which in plan view on a substrate, a plurality of pages are arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction,
each of the memory cells included in each of the pages comprising:
a semiconductor body that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction;
a first impurity region and a second impurity region that are disposed at respective ends of the semiconductor body;
a gate insulator layer that is in contact with a side surface of the semiconductor body between the first impurity region and the second impurity region;
a first gate conductor layer that partially or entirely covers the gate insulator layer; and
a second gate conductor layer that is adjacent to the first gate conductor layer and that is in contact with a side surface of the gate insulator layer, wherein
voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer are controlled to perform a page erase operation and a page write operation, and
in a page read operation, a first refresh operation, a second refresh operation, and a third refresh operation are performed, the first refresh operation being an operation of increasing the number of positive holes in a group of positive holes in the semiconductor body of a memory cell, in a page among the pages, in which logical “1” data is stored, by an impact ionization phenomenon caused by a current flowing from the second impurity region to the memory cell, the second refresh operation being an operation of making some of a group of positive holes in the semiconductor body of a memory cell, in a page among the pages, in which logical “0” data is stored disappear with a bit line pre-charge voltage retained in the second impurity region and by controlling the voltages applied to the first impurity region, the first gate conductor layer, and the second gate conductor layer and decreasing the number of positive holes,
the third refresh operation being an operation for the memory cell, in a page among the pages, in which the logical “1” data is stored, by using latch data in a sense amplifier circuit to which the second impurity region is connected with a switch circuit therebetween.
2. The semiconductor-element-including memory device according to claim 1 , wherein
the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a plate line, and
voltages applied to the source line, the bit line, the word line, and the plate line are controlled to perform the page write operation, the page erase operation, the page read operation, the first refresh operation, the second refresh operation, and the third refresh operation.
3. The semiconductor-element-including memory device according to claim 2 , wherein
the voltages applied to the source line, the bit line, the word line, and the plate line are controlled to perform the page erase operation of making some of a group of positive holes in the semiconductor body of each of the memory cells in a page among the pages disappear and decreasing the number of positive holes, and
to perform the page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell in a page among the pages.
4. The semiconductor-element-including memory device according to claim 2 , wherein
in the page read operation, the bit line pre-charge voltage is formed of charges that remain in the bit line of the memory cell in which the logical “0” data is stored.
5. The semiconductor-element-including memory device according to claim 1 , wherein
in the page erase operation, a voltage of the semiconductor body is made equal to a first data retention voltage, and
in the page write operation, the voltage of the semiconductor body is made equal to a second data retention voltage that is higher than the first data retention voltage.
6. The semiconductor-element-including memory device according to claim 2 , wherein
the word line and the plate line are disposed in parallel in plan view, and
the bit line is disposed in a direction perpendicular to the word line and the plate line in plan view.
7. The semiconductor-element-including memory device according to claim 2 , wherein
a first gate capacitance between the semiconductor body and the first gate conductor layer or the second gate conductor layer to which the plate line is connected is larger than a second gate capacitance between the semiconductor body and the first gate conductor layer or the second gate conductor layer to which the word line is connected.
8. The semiconductor-element-including memory device according to claim 2 , wherein
in plan view, the source line includes isolated source lines that are disposed for respective groups of memory cells arranged in the column direction and that are disposed parallel to the word line and the plate line.
9. The semiconductor-element-including memory device according to claim 2 , wherein
in plan view, the source line is disposed so as to be connected in common to all of the memory cells in pages adjacent to each other.
10. The semiconductor-element-including memory device according to claim 1 , wherein
the semiconductor body is a P-type semiconductor layer, and the first impurity region and the second impurity region are N-type semiconductor layers.
11. The semiconductor-element-including memory device according to claim 1 , wherein
in the page erase operation, selective erasing is performed for the memory cells in at least two pages.
12. The semiconductor-element-including memory device according to claim 1 , wherein
the first gate conductor layer is constituted by two divided gate conductor layers isolated from each other, and the divided gate conductor layers are positioned on respective sides of the second gate conductor layer, and
the page write operation, the page erase operation, the page read operation, the first refresh operation, the second refresh operation, and the third refresh operation are performed.
13. The semiconductor-element-including memory device according to claim 1 , wherein
the second gate conductor layer is constituted by two divided gate conductor layers isolated from each other, and the divided gate conductor layers are positioned on respective sides of the first gate conductor layer, and
the page write operation, the page erase operation, the page read operation, the first refresh operation, the second refresh operation, and the third refresh operation are performed.
14. The semiconductor-element-including memory device according to claim 2 , wherein
the word line and the plate line are connected to a row decoder circuit, the row decoder circuit receives a row address, and a page is selected from among the pages in accordance with the row address.
15. The semiconductor-element-including memory device according to claim 1 , wherein
the sense amplifier circuit is connected to a column decoder circuit, the column decoder circuit receives a column address, and the sense amplifier circuit is selectively connected to an input/output circuit in accordance with the column address.
16. The semiconductor-element-including memory device according to claim 2 , wherein
the sense amplifier circuit is a forced-inversion-type sense amplifier circuit, and the forced-inversion-type sense amplifier circuit has a sense node that is inverted when a current in the memory cell does not flow into the bit line.
17. The semiconductor-element-including memory device according to claim 2 , wherein
the first refresh operation and the second refresh operation are successively performed without a reset operation of changing the voltage applied to the plate line being performed.
18. The semiconductor-element-including memory device according to claim 1 , wherein
the third refresh operation is not performed each time the page read operation is performed.