IP Library › Granted Patent US 51,025
Granted Patent E1
US 51,025 · App. 18/222,335 · Granted Sep 8, 2026

Method and system for decoding

Inventors: Warren Gross (Montreal, CA); Saied Hemati (Montreal, CA); Shie Mannor (Montreal, CA); Ali Naderi (Montreal, CA); Francois Leduc-Primeau (Montreal, CA)
Assignee: Polar Technologies LLC
H03M13/1137H03M13/1117H03M13/1142H03M13/1151H03M13/3707H03M13/6544H03M13/6575H03M13/6577
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Quick Facts
Patent No.
US 51,025
App. No.
18/222,335
Granted
Sep 8, 2026
Kind
E1
Abstract

Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails.

Claims (128)

1 . A method comprising:

providing a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, wherein

at least one of:

(A) the decoder further comprises linking a common control line to a predetermined portion of the plurality of processing nodes wherein each processing node of the plurality of processing nodes comprises at least a control port coupled to the common control line for receiving a control message, and transmitting the control message on the common control line wherein the width of a pulse transmitted is modulated in dependence with a magnitude associated with the control message;

(B) the decoding process comprises estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process;

(C) the decoder further comprises providing a random number generator and executing a predetermined portion of the decoding process multiple times on the same received digital data wherein each execution is performed with a different seed for the random number generator;

(D) the decoder further comprises providing a second decoder comprising a component to randomize the decoding trajectory of the second decoder wherein digital content is parsed to the second decoder upon determining that the decoder has failed to decode the received digital data, the digital content being one of the decoded result of the decoder and the received digital data;

(E) the decoder further comprises providing a counter forming a predetermined portion of the decoder and operating the counter at a first clock rate, the first clock rate being at a higher clock rate than a second clock rate relating to the rest of the decoder;

(F) the decoder further comprises providing a variable node as part of the decoder, providing a check node as cart of the decoder, providing an edge linking the variable node and the check node and providing a clock having a first clock and a second clock rate wherein the clock is coupled to the variable node and the one of the first clock rate and second clock rate for the clock is established in dependence upon a transition relating to the edge; and

(G) the decoder further comprises a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes, a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes, and the decoding process comprises passing a current belief and information relating to the state of the plurality of processing nodes to an estimator to estimate a probability, delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes, and performing a parity check operation relating to the plurality of check nodes, the parity check operation made in dependence upon the level of agreement of the variable nodes.

2 . The method according to claim 1 further comprising;

providing a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

providing a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

determining a parity check relating to a predetermined subset of the plurality of check nodes in dependence upon a level of agreement between a predetermined subset of the plurality of variable nodes.

3 . The method according to claim 1 further comprising;

providing a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

providing a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes.

4 . A device comprising:

a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, the decoder comprising;

an estimator for estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process,

and further comprising at least one of:

(A) a common control line coupled to a predetermined portion of the plurality of processing nodes, each processing node of the plurality of processing nodes comprising at least a control port coupled to the common control line for receiving a control message, and a transmitter for transmitting the control message on the common control line wherein the width of a pulse transmitted is modulated in dependence with a magnitude associated with the control message;

(B) an estimator for estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process,

(C) a random number generator; and multiple executions of a predetermined portion of the decoding process multiple times on the same received digital data, each execution being performed with a different seed for the random number generator; and

(DC) a second decoder comprising a component to randomize the decoding trajectory of the second decoder; wherein digital content is parsed to the second decoder upon determining that the decoder has failed to decode the received digital data, the digital content being one of the decoded result of the decoder and the received digital data.

5 . The device according to claim 4 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

a parity checker for determining a parity check relating to a predetermined subset of the plurality of check nodes in dependence upon a level of agreement between a predetermined subset of the plurality of variable nodes.

6 . The device according to claim 4 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

a delay circuit for delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes.

7 . The device according to claim 4 further comprising;

a counter forming a predetermined portion of the decoder; wherein

the counter is operated at a first clock rate, the first clock rate being at a higher clock rate than a second clock rate relating to the rest of the decoder.

8 . The device according to claim 4 further comprising;

a variable node as part of the decoder;

a check node as part of the decoder;

an edge linking the variable node and the check node;

a clock generator for providing a clock having a first clock rate and a second clock rate to the variable node, the one of the first clock rate and second clock rate for the clock being determined in dependence upon a transition relating to the edge.

9 . The device according to claim 4 wherein,

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes;

an estimator for generating an estimate a probability in dependence upon a current belief and information relating to the state of the plurality of processing nodes;

a delay circuit for delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes; and

a parity checker for performing a parity check operation relating to the plurality of check nodes in dependence upon the level of agreement of the variable nodes.

10 . A device comprising:

a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, the decoder comprising an estimator for estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process,

and further comprising at least one of:

(A) a counter forming a predetermined portion of the decoder, wherein the counter is operated at a first clock rate, the first clock rate being at a higher clock rate than a second clock rate relating to the rest of the decoder;

(B) a variable node as part of the decoder, a check node as part of the decoder, an edge linking the variable node and the check node, and a clock generator coupled to the variable node for providing a clock having a first clock rate and a second clock rate, the one of the first clock rate and second clock rate being determined in dependence upon a transition relating to the edge; and

(C) a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes, a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes, an estimator for generating an estimate a probability in dependence upon a current belief and information relating to the state of the plurality of processing nodes, a delay circuit for delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes, and a parity checker for performing a parity check operation relating to the plurality of check nodes in dependence upon the level of agreement of the variable nodes.

11 . The device according to claim 10 further comprising;

a common control line coupled to a predetermined portion of the plurality of processing nodes, each processing node of the plurality of processing nodes comprising at least a control port coupled to the common control line for receiving a control message; and

a transmitter for transmitting the control message on the common control line wherein the width of a pulse transmitted is modulated in dependence with a magnitude associated with the control message.

12 . The device according to claim 10 further comprising;

an estimator for estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process.

13 . The device according to claim 10 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

a parity checker for determining a parity check relating to a predetermined subset of the plurality of check nodes in dependence upon a level of agreement between a predetermined subset of the plurality of variable nodes.

14 . The device according to claim 10 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

a delay circuit for delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes.

15 . The device according to claim 10 further comprising;

a random number generator; and

multiple executions of a predetermined portion of the decoding process multiple times on the same received digital data, each execution being performed with a different seed for the random number generator.

16 . The device according to claim 10 further comprising;

a second decoder comprising a component to randomize the decoding trajectory of the second decoder; wherein

digital content is parsed to the second decoder upon determining that the decoder has failed to decode the received digital data, the digital content being one of the decoded result of the decoder and the received digital data.

17. The method of claim 1 , wherein the decoder comprises a polar decoder.

18. The method of claim 17 , wherein the polar decoder decodes the digital data based on list decoding of at least one candidate codeword.

19. The method of claim 17 , further comprising a second decoder, the second decoder comprising a Low-Density Parity-Check (LDPC) decoder.

20. The method of claim 1 , wherein the decoder comprises a Low-Density Parity-Check (LDPC) decoder.

21. The method of claim 1 , wherein the plurality of processing nodes comprises a set of check nodes and a set of variable nodes.

22. The method of claim 21 , wherein the current belief is determined based on an output of at least one of the check nodes.

23. The method of claim 21 , wherein the number of check nodes is less than the number of variable nodes.

24. The method of claim 21 , wherein the probability is provided in a signal provided by at least one of the set of variable nodes.

25. The method of claim 21 , wherein the probability is provided in a signal provided by at least one of the set of check nodes.

26. The method of claim 1 , wherein the decoding process further comprises:

dividing the digital data into a first set of digital data and a second set of digital data;

decoding the first set of digital data using a first subset of the plurality of the processing nodes to obtain a first decoded result;

decoding the second set of digital data using a second subset of the plurality of processing nodes and a belief determined based on the first decoded result to obtain a second decoded result; and

constructing a decoded message based on the first decoded result and the second decoded result.

27. The method of claim 1 , further comprising receiving the digital data via a communication channel having data-corrupting noise present in the communication channel.

28. The method of claim 1 , wherein the decoding process comprises following distinct decoding paths within the plurality of processing nodes of the decoder.

29. The method of claim 28 , wherein the plurality of processing nodes comprises a set of variable nodes, a set of check nodes distinct from the set of variable nodes, and a plurality of associated edges, wherein a subset of the plurality of associated edges connects a variable node in the set of variable nodes to a check node in the set of check nodes.

30. The method of claim 29 , wherein the distinct decoding paths comprise combinations of variable nodes in the set of variable nodes, check nodes in the set of check nodes, and associated edges connecting a particular variable node to a particular check node.

31. The method of claim 29 , wherein a subset of the variable nodes are degree-3 variable nodes.

32. The method of claim 31 , wherein a second subset of the variable nodes are degree-1 variable nodes.

33. The method of claim 29 , wherein each of the check nodes are degree-1 check nodes.

34. The method of claim 1 , wherein the decoding process comprises obtaining a received signal vector of a first polar code.

35. The method of claim 34 , wherein the decoding process further comprises:

searching a codeword state space based on the received signal vector to identify a candidate codeword; and

constructing a decoded message based on the candidate codeword.

36. The method of claim 1 , wherein the current belief comprises a plurality of bits determined based on a subset of the plurality of processing nodes.

37. The method of claim 1 , wherein the estimated probability is determined based on an exclusive or operation performed on inputs to at least one of the plurality of processing nodes.

38. The method of claim 1 , wherein at least one of the plurality of processing nodes returns the current belief without any change to the states of the predetermined subset of the plurality of processing nodes.

39. The method of claim 1 , wherein each processing node in the plurality of processing nodes comprises an internal memory.

40. The method of claim 39 , wherein the internal memory of a particular processing node in the plurality of processing nodes stores the state of the particular processing node.

41. The method of claim 39 , wherein the internal memory of a particular processing node in the plurality of processing nodes stores the current belief of the particular processing node.

42. The method of claim 1 , wherein the plurality of processing nodes comprises a set of variable nodes, wherein at least one variable node in the set of variable nodes generates a signal updating the state of the predetermined subset of the plurality of processing nodes.

43. The method of claim 1 , wherein the plurality of processing nodes comprises a set of variable nodes, wherein at least one variable node in the set of variable nodes generates a signal updating the current belief.

44. The method of claim 1 , wherein the plurality of processing nodes comprises a set of check nodes, wherein each check node in the set of check nodes generates a signal having a predetermined value.

45. The method of claim 1 , wherein the plurality of processing nodes comprises a set of variable nodes, a set of check nodes, and a set of associated edges, wherein an edge connects a variable node to a check node if a codeword bit indicated in the variable node is included in a parity check equation indicated by the check node.

46. The method of claim 45 , wherein each edge in a variable node receives N inputs, where N-1 inputs are received from the variable node and one input is received from a bitstream generator.

47. the method of claim 46 , wherein the bitstream generator generates bits randomly with a given channel probability.

48. The method of claim 46 , wherein each edge calculates if its inputs are equal and generates an output, the output comprising a value of the inputs when the inputs are equal and the output comprising a randomly generated bit when the inputs are not equal.

49. The method of claim 45 , wherein:

a check node in the set of check nodes receives an input comprising a random bit, the states of a predetermined subset of the plurality of processing nodes, and the current belief; and

the check node generates an output signal based on the random bit, the states, and the current belief.

50. The method of claim 49 , wherein the output signal comprises the estimated probability.

51. The method of claim 1 , wherein the probability is provided in a signal provided by at least one of the plurality of processing nodes.

52. The method of claim 1 , wherein the probability is provided in a signal provided by at least one of the plurality of processing nodes.

53. The method of claim 1 , wherein the predetermined subset of the plurality of processing nodes comprises at least one processing node that has decoded a portion of the received digital data.

54. The method of claim 1 , wherein the predetermined subset of the plurality of processing nodes comprises at least one variable node.

55. The method of claim 1 , wherein the predetermined subset of the plurality of processing nodes comprises at least one check node.

56. The method of claim 1 , wherein the predetermined portion of the decoding process comprises a partial decoding of the received digital data.

57. The method of claim 1 , wherein the predetermined portion of the decoding process comprises a portion of the received digital data.

58. The method of claim 1 , wherein the predetermined portion of the decoding process comprises a parity check operation calculated based on the states of a predetermined subset of the plurality of processing nodes.

59. The method of claim 1 , wherein the predetermined portion of the decoding process comprises an equality check operation calculated based on the states of a predetermined subset of the plurality of processing nodes.

60. the method of claim 1 , further comprising a second decoder for decoding digital content according to the decoding process, the second decoder altering a trajectory of the decoding of the received digital data, the digital content being passed to the second decoder based on a state of the decoding of the received digital data by the decoder, the digital content comprising a decoded result of the received digital data by the decoder and the received digital data.

61. The method of claim 1 , further comprising:

detecting an error in a local codeword generated during the decoding process; and

removing the detected local codeword from the decoding process.

Continuity (5)
Provisional Application 61385602 · Sep 23, 2010
Provisional Application 61376801 · Aug 25, 2010
Provisional Application 61377114 · Aug 26, 2010
Provisional Application 61392544 · Oct 13, 2010
Reissue 13216373 · Aug 24, 2011
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