Semiconductor element memory cell and semiconductor element memory device
View Patent ↗By controlling voltages applied to plate lines, word lines, source lines, and bit lines, a memory device that uses semiconductor elements performs a data retention operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a memory erase operation of removing positive hole groups from inside the semiconductor base material. The memory device also performs a data erase operation during the memory erase operation to remove positive hole groups from inside the semiconductor base material of all the memory cells in a block made up of the memory cells, which are arrayed in a matrix.
1. A semiconductor element memory cell comprising:
a first impurity well layer formed on a substrate;
a second impurity well layer formed in the first impurity well layer;
a semiconductor base material formed on the second impurity well layer in a vertical direction or extended in a horizontal direction of the substrate;
a first impurity region and a second impurity region provided on opposite ends of the semiconductor base material;
first and second gate insulating layers placed adjacent to each other in contact with a lateral surface of the semiconductor base material between the first impurity region and the second impurity region;
a first gate conductor layer covering part or all of the first gate insulating layer; and
a second gate conductor layer located adjacent to the first gate conductor layer and placed in contact with a lateral surface of the second gate insulating layer,
wherein positive hole groups, generated by an impact ionization phenomenon or by a gate-induced drain leakage current, are held in the semiconductor base material by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region,
a memory write operation is performed by setting a voltage of the semiconductor base material to a first data retention voltage higher than a voltage of the first impurity region and/or the second impurity region, and
a memory erase operation is performed by controlling voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer and thereby extracting a residual positive hole group out of the positive hole groups from one or both of the first impurity region and the second impurity region to set the voltage of the semiconductor base material to a second data retention voltage lower than the first data retention voltage.
2. The semiconductor element memory cell according to claim 1 , wherein the substrate is a p-type semiconductor substrate, the first impurity well layer is an n-type semiconductor layer, and the second impurity well layer is a p-type semiconductor layer; and
a negative voltage is applied to the p-type second impurity well layer during the memory erase operation.
3. The semiconductor element memory cell according to claim 1 , wherein first gate capacitance between the first gate conductor layer and the semiconductor base material is higher than second gate capacitance between the second gate conductor layer and the semiconductor base material.
4. The semiconductor element memory cell according to claim 1 , wherein the memory erase operation is performed with respect to the semiconductor element memory cell by extracting a residual positive hole group out of the positive hole groups from one or both of the first impurity region and the second impurity region.
5. The semiconductor element memory device according to claim 1 , wherein:
the first impurity region is connected to a source line, the second impurity region is connected to a bit line, and one of the first gate conductor layer and the second gate conductor layer is connected to a word line and another is connected to a drive control line; and
using voltages applied to the source line, the bit line, the drive control line, and the word line, the memory erase operation and the memory write operation are performed selectively.
6. The semiconductor element memory device according to claim 1 , wherein:
a plurality of the semiconductor element memory cells is arrayed in a matrix, forming a block;
the semiconductor element memory device according to claim 1 further comprises a logical-physical conversion table configured to bring a physical address and a logical address of the block into correspondence with each other, and a controller circuit configured to manage the logical-physical conversion table; and
one or both of the logical-physical conversion table and the controller circuit is/are provided within or outside the block.
7. The semiconductor element memory device according to claim 6 , wherein a block erase operation involves applying an erase voltage to all source lines in the block and thereby putting the bit line in a floating state.
8. The semiconductor element memory device according to claim 7 , wherein:
at least one block is provided;
the semiconductor element memory device according to claim 7 further comprises an erase voltage generator circuit and a level conversion circuit; and
in the block erase operation, either an erase voltage outputted from the erase voltage generator circuit is applied to one or both of the first impurity region and the second impurity region in a selectively erased first block via the level conversion circuit and a residual positive hole group is extracted from the positive hole groups, thereby performing the block erase operation, or a ground voltage is applied to one or both of the first impurity region and the second impurity region in the second block which is not erased selectively, via the level conversion circuit, thereby not performing the block erase operation.
9. The semiconductor element memory device according to claim 1 , wherein one or both of the first gate conductor layer and the second gate conductor layer are divided into two or more separate gate conductor layers in planar view or in a vertical direction and the separate gate conductor layers are operated synchronously or asynchronously.
10. The semiconductor element memory device according to claim 9 , wherein in the vertical direction, either the separate gate conductor layers of the first gate conductor layer are placed on opposite sides of the second gate conductor layer, or the separate gate conductor layers of the second gate conductor layer are placed on opposite sides of the first gate conductor layer.
11. The semiconductor element memory device according to claim 7 , wherein the source lines are connected commonly in the block to perform the block erase operation.