Configurable cache for coherent system
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.
1. A device comprising:
a cache configuration register; and
a controller coupled to the cache configuration register, wherein the controller is configured to:
receive a pointer including a first pointer bit;
retrieve a first mask including a first mask bit from the cache configuration register;
retrieve a second mask including a second mask bit from the cache configuration register;
perform a first logical operation with the first pointer bit and the first mask bit to generate a first output bit;
perform a second logical operation with the first output bit and the second mask bit to generate a first way identifier bit; and
allocate a cache way to addressable memory space or data cache based on the first way identifier bit.
2. The device of claim 1 ,
wherein the pointer further includes a second pointer bit, and
wherein the controller is configured to allocate the cache way to addressable memory space or data cache based on the first way identifier bit and further based on the second pointer bit.
3. The device of claim 2 ,
wherein the first pointer bit is a least significant bit of the pointer, and
wherein the second pointer bit is a most significant bit of the pointer.
4. The device of claim 1 ,
wherein the pointer further includes a second pointer bit,
wherein the first mask further includes a third mask bit,
wherein the second mask further includes a fourth mask bit, and wherein the controller is configured to:
perform the first logical operation with the second pointer bit and the third mask bit to generate a second output bit;
perform the second logical operation with the second output bit and the fourth mask bit to generate a second way identifier bit; and
allocate the cache way to addressable memory space or data cache based on the first way identifier bit and further based on the second way identifier bit.
5. The device of claim 4 ,
wherein the first pointer bit is a first least significant bit of the pointer,
wherein the second pointer bit is a second least significant bit of the pointer,
wherein the pointer further includes a most significant pointer bit, and
wherein the controller is configured to allocate the cache way to addressable memory space or data cache based on the first way identifier bit and the second way identifier bit and further based on the most significant pointer bit.
6. The device of claim 5 ,
wherein the most significant pointer bit is a first most significant pointer bit,
wherein the pointer further includes a second most significant pointer bit, and
wherein the controller is configured to allocate the cache way to addressable memory space or data cache based on the first way identifier bit, the second way identifier bit, the first most significant pointer bit and further based on the second most significant pointer bit.
7. The device of claim 1 ,
wherein the controller is configured to receive a memory access request associated with a cache tag, and
wherein the controller is configured to allocate the cache way to the cache tag based on the first way identifier bit.
8. The device of claim 7 , wherein the controller is configured to:
receive the memory access request from a requesting device, and
retrieve the first mask and the second mask based on whether the requesting device is associated with real-time or non-real-time.
9. The device of claim 1 , wherein the controller is configured to allocate the cache way to addressable memory space by at least allocating the cache way to scratch pad memory rather than to data cache.
10. The device of claim 1 ,
wherein the first mask is an AND mask, and
wherein the first logical operation is an AND operation.
11. The device of claim 1 ,
wherein the first mask is an OR mask, and
wherein the first logical operation is an OR operation.
12. The device of claim 1 , wherein the pointer is a randomly generated pointer.
13. A method comprising:
receiving, at a controller, a pointer including a first pointer bit;
retrieving, by the controller, a first mask including a first mask bit from a cache configuration register;
retrieving, by the controller, a second mask including a second mask bit from the cache configuration register;
performing, by the controller, a first logical operation with the first pointer bit and the first mask bit to generate a first output bit;
performing, by the controller, a second logical operation with the first output bit and the second mask bit to generate a first way identifier bit; and
allocating, by the controller, a cache way to addressable memory space or data cache based on the first way identifier bit.
14. The method of claim 13 ,
wherein the pointer further includes a second pointer bit, and
wherein allocating the cache way to addressable memory space or data cache is based on the first way identifier bit and further based on the second pointer bit.
15. The method of claim 13 ,
wherein the pointer further includes a second pointer bit,
wherein the first mask further includes a third mask bit,
wherein the second mask further includes a fourth mask bit, and
wherein the method further comprises:
performing the first logical operation with the second pointer bit and the third mask bit to generate a second output bit; and
performing the second logical operation with the second output bit and the fourth mask bit to generate a second way identifier bit,
wherein allocating the cache way to addressable memory space or data cache is based on the first way identifier bit and further based on the second way identifier bit.
16. The method of claim 15 ,
wherein the first pointer bit is a first least significant bit of the pointer,
wherein the second pointer bit is a second least significant bit of the pointer,
wherein the pointer further includes a most significant pointer bit, and
wherein allocating the cache way to addressable memory space or data cache is based on the first way identifier bit and the second way identifier bit and further based on the most significant pointer bit.
17. The method of claim 16 ,
wherein the most significant pointer bit is a first most significant pointer bit,
wherein the pointer further includes a second most significant pointer bit, and
wherein allocating the cache way to addressable memory space or data cache is based on the first way identifier bit, the second way identifier bit, the first most significant pointer bit and further based on the second most significant pointer bit.
18. The method of claim 13 , further comprising receiving a memory access request associated with a cache tag, and
wherein allocating the cache way comprises allocating the cache way to the cache tag is based on the first way identifier bit.
19. The method of claim 18 ,
wherein receiving the memory access request comprises receiving the memory access request from a requesting device, and
wherein retrieving the first mask and the second mask is based on whether the requesting device is associated with real-time or non-real-time.
20. The method of claim 13 , wherein allocating the cache way to addressable memory space comprises allocating the cache way to scratch pad memory rather than to data cache.