Read control signal generation for memory

1. A memory device comprising:

memory comprised of a bank area and a channel area; and

control circuitry configured to:

receive a command to access the memory; and

responsive to receiving the command to access the memory:

provide a bank control path and a channel control path;

provide a bank strobe signal over the bank control path for accessing the memory in the bank area; and

provide at least two channel strobe signals over the channel control path for accessing the memory in the channel area;

wherein the bank control path comprises disable circuitry configured to selectively disable one or more bank strobe signals.

2. The memory device of claim 1 , wherein a channel strobe signal of the at least two channel strobe signals processes a smaller amount of data than that processed by the bank strobe signal.

3. The memory device of claim 2 , wherein the channel strobe signal processes one half an amount of data that the bank strobe signal processes.

4. The memory device of claim 1 , wherein the disable circuitry comprises delay circuitry for providing a disabling pulse delayed by an offset subsequent to the bank strobe signal.

5. The memory device of claim 1 , wherein the disable circuitry is configured to disable one bank strobe signal for every other channel strobe signal provided.

6. The memory device of claim 1 , wherein the disable circuitry is configured to refrain from disabling the bank strobe signal during mask write operations.

7. The memory device of claim 1 , wherein the disable circuitry is configured to refraining from disabling the bank strobe signal during internal read operations.

8. The memory device of claim 1 , wherein the memory comprises ferroelectric random access memory (FeRAM) or dynamic random access memory (DRAM).

9. A system comprising:

a host device;

memory comprising a bank area, a bank control path, a channel area, and a channel control path, wherein the bank control path comprises disable circuitry configured to selectively disable one or more bank strobe signals; and

control circuitry configured to:

receive a command to access the memory; and

responsive to receiving the command to access the memory:

provide a bank strobe signal over the bank control path for accessing memory in the bank area; and

provide at least two channel strobe signals over the channel control path for accessing memory in the channel area.

10. The system of claim 9 , wherein a channel strobe signal of the at least two channel strobe signals processes one half an amount of data of the bank strobe signal.

11. The system of claim 9 , wherein the disable circuitry is configured to disable one bank strobe signal for every other channel strobe signal provided.

12. The system of claim 11 , wherein the disable circuitry is configured to refraining from disabling the bank strobe signal during mask read operations.

13. The system of claim 9 , wherein the memory comprises ferroelectric random access memory (FeRAM) or dynamic random access memory (DRAM).

14. A method comprising:

receiving a command to access a memory; and

responsive to receiving the command to access the memory:

providing a bank strobe signal over a bank control path for accessing memory in a bank area of the memory; and

providing at least two channel strobe signals over the channel control path for accessing memory in a channel area of the memory; and

disabling a number of bank strobe signals.

15. The method of claim 14 , wherein a channel strobe signal of the at least two channel strobe signals processes one half an amount of data of the bank strobe signal.

16. The method of claim 14 , further comprising suppressing one bank strobe signal for every other channel strobe signal provided.

17. The method of claim 16 , further comprising refraining from disabling the bank strobe signal during mask read operations.