SYSTEMS AND METHODS FOR BALANCING MEMORY SPEEDS
Systems and methods for balancing memory speeds are disclosed. In particular, at start up, a host to memory bus speed is determined and compared to a default internal memory device bus speed. A memory device control circuit may then determine if an internal bus should be overclocked or slowed down to match the host to memory bus speed. The selection may then be stored in a register and made available to a host memory controller (e.g., through polling or the like). Selection of an internal speed may also be based on other factors such as power savings or the like. In either event, having the flexibility to set the internal speed based on one or more such criteria may result in improved efficiency.
1 . A memory device comprising:
an external bus interface configured to couple to a bus having a first speed;
an internal bus;
a memory circuit coupled to the internal bus and having a second speed;
a control circuit coupled to the internal bus and the external bus interface, the control circuit configured to:
compare the first speed to the second speed;
change the second speed to match approximately the first speed.
2 . The memory device of claim 1 , wherein the control circuit is configured to overclock the memory circuit to change the second speed to match the first speed.
3 . The memory device of claim 1 , wherein the control circuit is configured to change a divide by M circuit coupled to a clock to change the second speed to match the first speed.
4 . The memory device of claim 1 , wherein the control circuit is configured to slow down the second speed to match the first speed.
5 . The memory device of claim 1 , wherein the external bus interface comprises a peripheral component interconnect express (PCIe) bus interface or compute express link (CXL) enabled PCIe bus interface.
6 . The memory device of claim 1 , wherein the memory circuit comprises a dynamic random access memory (DRAM) memory circuit.
7 . The memory device of claim 6 , wherein the DRAM memory circuit comprises a double data rate (DDR) version 4 (DDR4) memory circuit.
8 . The memory device of claim 1 , further comprising a plurality of memory circuits.
9 . The memory device of claim 1 , further comprising a register coupled to the control circuit.
10 . The memory device of claim 9 , wherein the control circuit is configured to store the second speed in the register after changing the second speed to match the first speed.
11 . A method of balancing speeds for a memory device, the method comprising:
determining a first speed associated with an external bus coupled to the memory device;
determining a second speed associated with a memory circuit in the memory device; and
changing the second speed to match approximately the first speed.
12 . The method of claim 11 , wherein changing the second speed comprises overclocking the memory circuit.
13 . The method of claim 11 , wherein changing the second speed to match the first speed comprises adjusting a divide by M circuit coupled to a clock.
14 . The method of claim 11 , wherein changing the second speed to match the first speed comprises slowing down the memory circuit.
15 . The method of claim 11 , further comprising storing the second speed in a register after changing the second speed to match the first speed.
16 . The method of claim 15 , further comprising providing the second speed from the register to a remote host after storing.
17 . The method of claim 16 , wherein providing the second speed comprises providing the second speed responsive to the remote host polling the register.