IP Library Granted Patent US 12,189,554
Granted Patent B2
US 12,189,554 · App. 18/239,042 · Granted Jan 7, 2025

Adaptive interface storage device with multiple storage protocols including solid state drive storage devices

Inventors: Stephen G. Fischer (Mountain View, CA); Sompong Paul Olarig (Pleasanton, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F13/287G06F3/061G06F3/0655G06F3/0685G06F13/4208G06F13/00G06F2213/0026
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Quick Facts
Patent No.
US 12,189,554
App. No.
18/239,042
Granted
Jan 7, 2025
Kind
B2
Abstract

An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.

Claims (35)

1. A device comprising:

a connector configured to receive signal having one of a first value or a second value;

first circuitry, wherein based on the signal having the first value, first configuration data is selected to configure the first circuitry to operate according to a first protocol, and based on the signal having the second value, second configuration data is selected to configure the first circuitry to operate according to a second protocol; and

second circuitry coupled to the connector and the first circuitry, wherein based on the signal having the first value, a first portion of the second circuitry is selected for connecting to a first portion of the first circuitry to provide a first type of interface, and based on the signal having a second value, a second portion of the second circuitry is selected for connecting to a second portion of the first circuitry to provide a second type of interface.

2. The device of claim 1 , wherein the connector includes a connector for a solid state drive.

3. The device of claim 1 , wherein the first circuitry includes a field programmable gate array.

4. The device of claim 1 , wherein the first protocol is for receiving first storage commands over a data communications bus, and the second protocol is for receiving second storage commands over a network.

5. The device of claim 1 , wherein the second circuitry includes routing or switching circuitry.

6. The device of claim 5 , wherein the first portion of the second circuitry includes one or more first interfaces of the routing or switching circuitry, and the second portion of the second circuitry includes one or more second interfaces of the routing or switching circuitry.

7. The device of claim 6 , wherein the first portion of the first circuitry includes one or more first communication channels, and the second portion of the first circuitry includes one or more second communication channels.

8. The device of claim 1 , wherein the first type of interface is for communicating with at least one of a storage device or a computing device according to the first protocol, and the second type of interface is for communicating with at least one of the storage device or the computing device according to the second protocol.

9. The device of claim 1 further comprising:

third circuitry connected to the first circuitry, wherein the signal having the first value is configured to cause the third circuitry to select the first configuration data stored in a first memory, and the signal having the second value is configured to cause the third circuitry to select the second configuration data stored in a second memory.

10. The device of claim 9 , wherein the first circuitry includes an interface, wherein the third circuitry is configured to connect the interface to the first memory based on the signal having the first value for retrieving the first configuration data from the first memory, and is further configured to connect the interface to the second memory based on the signal having the second value for retrieving the second configuration data from the second memory.

11. A method comprising:

receiving, via a connector, a signal having one of a first value or a second value;

based on the signal having the first value:

selecting first configuration data for configuring a first circuitry to operate the first circuitry according to a first protocol;

selecting a first portion of second circuitry coupled to the connector and the first circuitry, wherein the first portion of the second circuitry is selected for connecting to a first portion of the first circuitry to provide a first type of interface;

based on the signal having a second value:

selecting second configuration data for configuring the first circuitry to operate the first circuitry according to a second protocol; and

selecting a second portion of the second circuitry for connecting to a second portion of the first circuitry to provide a second type of interface.

12. The method of claim 11 , wherein the connector includes a connector for a solid state drive.

13. The method of claim 11 , wherein the first circuitry includes a field programmable gate array.

14. The method of claim 11 , wherein the first protocol is for receiving first storage commands over a data communications bus, and the second protocol is for receiving second storage commands over a network.

15. The method of claim 11 , wherein the second circuitry includes routing or switching circuitry.

16. The method of claim 15 , wherein the first portion of the second circuitry includes one or more first interfaces of the routing or switching circuitry, and the second portion of the second circuitry includes one or more second interfaces of the routing or switching circuitry.

17. The method of claim 16 , wherein the first portion of the first circuitry includes one or more first communication channels, and the second portion of the first circuitry includes one or more second communication channels.

18. The method of claim 11 , wherein the first type of interface is for communicating with at least one of a storage device or a computing device according to the first protocol, and the second type of interface is for communicating with at least one of the storage device or the computing device according to the second protocol.

19. The method of claim 11 further comprising:

selecting, via a third circuitry connected to the first circuitry, the first configuration data stored in a first memory based on the signal having the first value; and

selecting, via the second circuitry, the second configuration data stored in a second memory based on the signal having the second value.

20. The method of claim 19 , wherein the first circuitry includes an interface, the method further comprising:

connecting the interface to the first memory based on the signal having the first value for retrieving the first configuration data from the first memory; and

connecting the interface to the second memory based on the signal having the second value for retrieving the second configuration data from the second memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2023
From: FISCHER, STEPHEN G.; OLARIG, SOMPONG PAUL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 064980/0102 →
Continuity (5)
Continuation 17156434 · Jan 22, 2021
Continuation 16696649 · Nov 26, 2019
Continuation 16020923 · Jun 27, 2018
Provisional Application 62641246 · Mar 9, 2018
Related Publication 20230401165A1 · Dec 14, 2023
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