Semiconductor device and data storage systems including a semiconductor device
A semiconductor device including a first semiconductor structure overlapping a second semiconductor structure, the second semiconductor structure having first and second regions and including a plate layer; gate electrodes spaced apart from each other in a first direction; channel structures passing through the gate electrodes; gate separation regions extending in a second direction; first and second upper isolation regions dividing an upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions; and contact plugs extending in the first direction, each of the first and second upper isolation regions has a region extending in a third direction, and the first sub-gate electrode has a first pad region having a first width and a second pad region having a second width narrower than the first width in a fourth direction, and the first sub-gate electrode is connected to one of the contact plugs.
1 . A semiconductor device comprising:
a first semiconductor structure including a substrate, circuit elements on the substrate, and circuit interconnection lines connected to the circuit elements; and
a second semiconductor structure on the first semiconductor structure, the second semiconductor structure having first and second regions,
wherein the second semiconductor structure includes:
a plate layer;
gate electrodes stacked on the plate layer and spaced apart from each other in a first direction, perpendicular to an upper surface of the plate layer, the gate electrodes including a lower gate electrode, memory gate electrodes, and an upper gate electrode sequentially stacked, and the gate electrodes having pad regions extending to different lengths in a second direction, perpendicular to the first direction, in the second region such that upper surfaces of the pad regions are exposed;
channel structures, in the first region, the channel structures passing through the gate electrodes, extending in the first direction, and each including a channel layer;
gate separation regions, in the first and second regions, the gate separation regions passing through the gate electrodes and extending in the second direction;
first and second upper isolation regions on the memory gate electrodes, the first and second upper isolation regions dividing the upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions, and extending in the second direction; and
contact plugs, in the second region, the contact plugs extending in the first direction through the pad regions of the gate electrodes, and connected to portions of the circuit interconnection lines,
each of the first and second upper isolation regions has a region extending in a third direction, intersecting the second direction, and
the first sub-gate electrode has a first pad region having a first width and a second pad region having a second width narrower than the first width in a fourth direction, perpendicular to the second direction, and the first sub-gate electrode is connected to one of the contact plugs in the first pad region.
2 . The semiconductor device of claim 1 , wherein the first and second upper isolation regions have shapes symmetrical to each other in the fourth direction.
3 . The semiconductor device of claim 1 , wherein the second sub-gate electrode has a third pad region parallel to the first pad region in the fourth direction and a fourth pad region parallel to the second pad region in the fourth direction, and the second sub-gate electrode is connected to one of the contact plugs in the fourth pad region.
4 . The semiconductor device of claim 3 , wherein, in the second sub-gate electrode, the third pad region has a third width in the fourth direction, and the fourth pad region has a fourth width wider than the third width and the first width in the fourth direction.
5 . The semiconductor device of claim 1 , wherein the first and second upper isolation regions extend in the second direction in the first region, and extend in the second direction and the third direction in the second region, adjacent to the first region.
6 . The semiconductor device of claim 1 , wherein the third direction is a direction the same as the fourth direction or a direction between the second direction and the fourth direction.
7 . The semiconductor device of claim 1 , wherein the memory gate electrodes and the lower gate electrode horizontally extend below the first and second upper isolation regions.
8 . The semiconductor device of claim 1 , wherein
the first, second and third sub-gate electrodes are respectively connected to first, second and third contact plugs, among the contact plugs, and
at least portions of the first, second and third contact plugs do not overlap each other in the fourth direction.
9 . The semiconductor device of claim 1 , wherein each of the contact plugs includes a vertical extension extending in the first direction and a horizontal extension horizontally extending from the vertical extension and in contact with one of the pad regions.
10 . The semiconductor device of claim 1 , wherein the second semiconductor structure further includes contact insulating layers on levels the same as levels of the gate electrodes and at side surfaces of the contact plugs.
11 . The semiconductor device of claim 1 , wherein the second semiconductor structure further includes support structures passing through the gate electrodes and portions of the first and second upper isolation regions around the contact plugs.
12 . The semiconductor device of claim 11 , wherein at least one of the support structures passes through the second pad region.
13 . The semiconductor device of claim 1 , wherein the upper gate electrode forms a string selection transistor.
14 . A semiconductor device comprising:
a first semiconductor structure including a substrate, circuit elements on the substrate, and circuit interconnection lines connected to the circuit elements; and
a second semiconductor structure on the first semiconductor structure and having first and second regions,
wherein the second semiconductor structure includes:
a plate layer;
gate electrodes stacked on the plate layer and spaced apart from each other in a first direction, perpendicular to an upper surface of the plate layer, and having pad regions extending to different lengths in a second direction, perpendicular to the first direction, in the second region such that upper surfaces of the pad regions are exposed;
gate separation regions, in the first and second regions, passing through the gate electrodes and extending in the second direction;
an upper isolation region on portions of the gate electrodes, dividing an uppermost gate electrode, among the gate electrodes, into first and second sub-gate electrodes between the gate separation regions, and extending in the second direction, and
contact plugs, in the second region, extending in the first direction through the gate electrodes and connected to portions of the circuit interconnection lines,
the upper isolation region has a region extending in a third direction, intersecting the second direction,
the first sub-gate electrode has first and second pad regions having different sizes, and the second sub-gate electrode has third and fourth pad regions having different sizes, and
the first sub-gate electrode is connected to one of the contact plugs in the first pad region, and the second sub-gate electrode is connected to one of the contact plugs in the fourth pad region.
15 . The semiconductor device of claim 14 , wherein the first pad region is parallel to the third pad region, and the second pad region is parallel to the fourth pad region, in a fourth direction, perpendicular to the second direction.
16 . The semiconductor device of claim 14 , wherein a size of the first pad region is larger than a size of the second pad region, and a size of the third pad region is smaller than a size of the fourth pad region.
17 . The semiconductor device of claim 14 , wherein a size of the first pad region is different from a size of the fourth pad region.
18 . The semiconductor device of claim 14 , wherein a lower end of the upper isolation region is on a level between two gate electrodes, vertically adjacent to each other, among the gate electrodes.
19 . A data storage system comprising:
a semiconductor storage device including a first semiconductor structure including circuit elements, a second semiconductor structure including channel structures and having first and second regions, and an input/output pad electrically connected to the circuit elements; and
a controller electrically connected to the semiconductor storage device via the input/output pad and configured to control the semiconductor storage device,
wherein the second semiconductor structure further includes:
gate electrodes stacked and spaced apart from each other in a first direction, the gate electrodes including a lower gate electrode, memory gate electrodes, and an upper gate electrode sequentially stacked, and having pad regions extending to different lengths in a second direction, perpendicular to the first direction, in the second region such that upper surfaces of the pad regions are exposed;
gate separation regions, in the first and second regions, passing through the gate electrodes and extending in the second direction;
first and second upper isolation regions on the memory gate electrodes, dividing the upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions, and extending in the second direction; and
contact plugs, in the second region, extending in the first direction through the pad regions of the gate electrodes and connected to portions of the circuit interconnection lines, and
the first and second upper isolation regions have regions extending in a third direction, intersecting the second direction, and being symmetrical to each other in a fourth direction, perpendicular to the second direction.
20 . The data storage system of claim 19 , wherein the first sub-gate electrode has a first pad region having a first width and a second pad region having a second width narrower than the first width in the fourth direction, and is connected to one of the contact plugs in the first pad region.