IP Library › Granted Patent US 12,243,577
Granted Patent B2
US 12,243,577 · App. 18/242,155 · Granted Mar 4, 2025

Automated voltage demarcation (VDM) adjustment for memory device

Inventors: Yi-Min Lin (San Jose, CA); Fangfang Zhu (San Jose, CA); Chih-Kuo Kao (Fremont, CA)
Assignee: Micron Technology, Inc.
G11C11/4074G11C11/4076G11C11/4096G11C29/42
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Quick Facts
Patent No.
US 12,243,577
App. No.
18/242,155
Granted
Mar 4, 2025
Kind
B2
Abstract

A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.

Claims (55)

1. A system comprising:

a memory device;

a processing device, operatively coupled to the memory device, the processing device configured to:

receive a plurality of codewords;

determine that one or more codewords of the plurality of codewords are corrupt;

select a first read voltage associated with the one or more codewords, wherein the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords and a second read voltage utilized for reading the one or more codewords in a previous read operation; and

apply the first read voltage to a set of memory cells storing the one or more codewords.

2. The system of claim 1 , wherein the processing device is further configured to:

responsive to applying the first read voltage to the set of memory cells, perform an error correction operation on the one or more codewords.

3. The system of claim 1 , wherein the processing device is further configured to:

responsive to determining that a number of recovery operations performed with respect to the one or more codewords is below a threshold number, select a third read voltage exceeding the first read voltage; and

apply the third read voltage to the set of memory cells.

4. The system of claim 1 , wherein the processing device is further configured to:

responsive to determining that a number of recovery operations performed with respect to the one or more codewords is equal or exceeds a threshold number, determine a respective error status for each codeword of the one or more codewords.

5. The system of claim 1 , wherein determining that the one or more codewords are corrupt further comprises:

detecting one or more errors returned by an error correction operation performed with respect to the one or more codewords.

6. The system of claim 1 , wherein the first read voltage exceeds the second read voltage.

7. The system of claim 1 , wherein the processing device is further configured to:

responsive to determining that the first read voltage is below a maximum read voltage, select a third read voltage exceeding the first read voltage; and

apply the third read voltage to the set of memory cells.

8. A method, comprising:

receiving, by a processing device, a plurality of codewords;

determining that one or more codewords of the plurality of codewords are corrupt;

selecting a first read voltage associated with the one or more codewords, wherein the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords and a second read voltage utilized for reading the one or more codewords in a previous read operation; and

applying the first read voltage to a set of memory cells storing the one or more codewords.

9. The method of claim 8 , further comprising:

responsive to applying the first read voltage to the set of memory cells, performing an error correction operation on the one or more codewords.

10. The method of claim 8 , further comprising:

responsive to determining that a number of recovery operations performed with respect to the one or more codewords is below a threshold number, selecting a third read voltage exceeding the first read voltage; and

applying the third read voltage to the set of memory cells.

11. The method of claim 8 , further comprising:

responsive to determining that a number of recovery operations performed with respect to the one or more codewords is equal or exceeds a threshold number, determining a respective error status for each codeword of one or more codewords.

12. The method of claim 8 , wherein determining that the one or more codewords are corrupt further comprises:

detecting one or more errors returned by an error correction operation performed with respect to the one or more codewords.

13. The method of claim 8 , wherein the first read voltage exceeds the second read voltage.

14. The method of claim 8 , further comprising:

responsive to determining that the first read voltage is below a maximum read voltage, selecting a third read voltage exceeding the first read voltage; and

applying the third read voltage to the set of memory cells.

15. A non-transitory computer-readable storage medium comprising executable instructions, which when executed by a processing device, cause the processing device to:

receive a plurality of codewords;

determine that one or more codewords of the plurality of codewords are corrupt;

select a first read voltage associated with the one or more codewords, wherein the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords and a second read voltage utilized for reading the one or more codewords in a previous read operation; and

apply the first read voltage to a set of memory cells storing the one or more codewords.

16. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions, which when executed by the processing device, cause the processing device to:

responsive to applying the first read voltage to the set of memory cells, perform an error correction operation on the one or more codewords.

17. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions, which when executed by the processing device, cause the processing device to:

responsive to determining that a number of recovery operations performed with respect to the one or more codewords is below a threshold number, select a third read voltage exceeding the first read voltage; and

apply the third read voltage to the set of memory cells.

18. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions, which when executed by the processing device, cause the processing device to:

responsive to determining that a number of recovery operations performed with respect to the one or more codewords is equal or exceeds a threshold number, determine a respective error status for each codeword of the one or more codewords.

19. The non-transitory computer-readable storage medium of claim 15 , wherein determining that the one or more codewords are corrupt further comprises:

detecting one or more errors returned by an error correction operation performed with respect to the one or more codewords.

20. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions, which when executed by the processing device, cause the processing device to:

responsive to determining that the first read voltage is below a maximum read voltage, select a third read voltage exceeding the first read voltage; and

apply the third read voltage to the set of memory cells.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2023
From: LIN, YI-MIN; ZHU, FANGFANG; KAO, CHIH-KUO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 064796/0042 →
Continuity (2)
Division 17463274 · Aug 31, 2021
Related Publication 20230410878A1 · Dec 21, 2023
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