IP Library › Granted Patent US 12,277,075
Granted Patent B2
US 12,277,075 · App. 18/251,672 · Granted Apr 15, 2025

Memory request priority up-leveling

Inventors: Nagaraj Ashok Putti (Bangalore, IN); Gopi Neela (Bengaluru, IN); Shubham Mahajan (Bangalore, IN); Praxal Sunilkumar Shah (Ahmedabad, IN)
Assignee: Google LLC
G06F13/1673
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,277,075
App. No.
18/251,672
Granted
Apr 15, 2025
Kind
B2
Abstract

The described techniques and apparatuses enable memory-request priority up-leveling. A memory request is received over a virtual channel, VC, and is then added to a memory-request buffer with an original priority-level for the memory request and an indication that the memory request is associated with a virtual channel identification, VCID, of the VC. Related memory requests within the memory-request buffer are also indicated as being associated with the VCID. Responsive to determining that an up-level indication for the VCID is asserted over a side channel, the original priority-levels of the memory request, and other memory-requests in the memory-request buffer having an indication of the VCID, are increased to respective up-leveled priority levels. Responsive to determining that the up-level indication is no longer asserted, the up-leveled priority levels are returned to respective original priority-levels.

Claims (50)

1. A method for memory request priority adjustment performed by a memory controller, the method comprising:

receiving a memory request from a client over a virtual channel, VC, the memory request having an original priority-level;

adding the memory request to a memory request buffer along with:

an indication of a virtual channel identification, VCID, of the VC; and

the original priority-level for the memory request;

determining if another memory request in the memory request buffer is related to the memory request by comparing a transaction identification of the memory request to respective transaction identifications for other memory requests within the memory request buffer or comparing one or more memory addresses of the memory request to respective memory addresses for other memory requests within the memory request buffer;

determining that an adjustment indication corresponding to the VCID is asserted; and

increasing or decreasing the original priority-level of the memory request to an adjusted priority level based on the asserted adjustment indication.

2. The method of claim 1 , wherein the adjustment indication is asserted via a side channel to the memory controller.

3. The method of claim 1 , wherein the adjustment indication is asserted from the client or another client using the VC.

4. The method of claim 1 , further comprising determining an adjustment amount comprising:

an amount by which to increase or decrease the original priority-level; or

a value for the adjusted priority level.

5. The method of claim 1 , further comprising:

determining that the adjustment indication is no longer asserted; and

responsive to the determining that the adjustment indication is no longer asserted, returning the adjusted priority level of the memory request to the original priority-level.

6. The method of claim 1 , further comprising granting the memory request based on the adjusted priority level.

7. The method of claim 1 , wherein the original priority-level is assigned by the client.

8. The method of claim 1 , wherein the VC is based on the client.

9. The method of claim 1 , wherein the other memory requests were received over one or more VCs that are different than the VC.

10. The method of claim 1 , further comprising, responsive to determining that one of the other memory requests is a related memory request that is related to the memory request, assigning the VCID to the related memory request.

11. The method of claim 1 , further comprising:

determining that one or more other memory requests within the memory request buffer have an indication of the VCID; and

increasing or decreasing, based on the adjustment indication, respective original priority-levels of the other memory requests to respective adjusted priority levels.

12. A memory controller comprising:

an interface configured to operably couple the memory controller to a client via a virtual channel (VC);

a memory request buffer; and

a memory request priority-level adjustment module configured to:

receive a memory request from the client over the VC, the memory request having an original priority-level;

add the memory request to the memory request buffer along with:

an indication of a virtual channel identification, VCID, of the VC; and

the original priority-level for the memory request;

determine if another memory request in the memory request buffer is related to the memory request by comparing a transaction identification of the memory request to respective transaction identifications for other memory requests within the memory request buffer or comparing one or more memory addresses of the memory request to respective memory addresses for other memory requests within the memory request buffer;

determine that an adjustment indication corresponding to the VCID is asserted; and

increase or decrease the original priority-level of the memory request to an adjusted priority level based on the asserted adjustment indication.

13. The memory controller of claim 12 , wherein the adjustment indication is asserted via a side channel to the memory controller.

14. The memory controller of claim 12 , wherein the adjustment indication is asserted from the client or another client using the VC.

15. The memory controller of claim 12 , wherein the memory request priority-level adjustment module is further configured to determine an adjustment amount for the memory request based on:

an amount by which to increase or decrease the original priority-level; or

a value for the adjusted priority level.

16. The memory controller of claim 12 , wherein the memory request priority-level adjustment module is further configured to:

determine that the adjustment indication is no longer asserted; and

responsive to the determination that the adjustment indication is no longer asserted, return the adjusted priority level of the memory request to the original priority-level.

17. The memory controller of claim 12 , wherein the memory controller is configured to grant the memory request based on the adjusted priority level.

18. The memory controller of claim 12 , wherein:

the original priority-level is assigned by the client; or

the VC is based on the client.

19. The memory controller of claim 12 , wherein the other memory requests were received over one or more other VCs that are different than the VC.

20. The memory controller of claim 12 , wherein the memory request priority-level adjustment module is further configured to:

in response to determining that one of the other memory requests is a related memory request that is related to the memory request, assign the VCID to the related memory request.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2023
From: PUTTI, NAGARAJ ASHOK; NEELA, GOPI; MAHAJAN, SHUBHAM; SHAH, PRAXAL SUNILKUMAR
To: GOOGLE LLC
Reel/Frame 063950/0571 →
Continuity (1)
Related Publication 20240012771A1 · Jan 11, 2024
References Cited (26)
US 8690475B2 · Springer · 2014 [cited by examiner]
US 9405688B2 · Nagarajan et al. · 2016 [cited by applicant]
US 9535860B2 · Cutter et al. · 2017 [cited by applicant]
US 10223298B2 · Chhabra et al. · 2019 [cited by applicant]
US 10250510B2 · Sridharan · 2019 [cited by examiner]
US 10838884B1 · Magudilu Vijavaraj · 2020 [cited by examiner]
US 11003602B2 · Walker · 2021 [cited by examiner]
US 20050058130A1 · Christ · 2005 [cited by examiner]
US 20120311277A1 · Chu et al. · 2012 [cited by applicant]
US 20150317266A1 · Kramer · 2015 [cited by examiner]
US 20160364303A1 · Gilda et al. · 2016 [cited by applicant]
US 20180210847A1 · Walker · 2018 [cited by applicant]
US 20190012209A1 · Chiou et al. · 2019 [cited by applicant]
US 20190012290A1 · Watanabe · 2019 [cited by applicant]
US 20200285420A1 · Guim Bernat · 2020 [cited by examiner]
US 20200301859A1 · Chin · 2020 [cited by applicant]
CN 103914412A · 2014 [cited by applicant]
CN 106445628 · 2017 [cited by applicant]
CN 110214316A · 2019 [cited by applicant]
JP 2020154697A · 2020 [cited by applicant]
TW 201635150 · 2016 [cited by applicant]
TW 201702882 · 2017 [cited by applicant]
WO 2022098356 · 2022 [cited by applicant]
“International Preliminary Report on Patentability”, Application No. PCT/US2020/059061, May 8, 2023, 7 pages. [cited by applicant]
“International Search Report and Written Opinion”, Application No. PCT/US2020/059061, May 25, 2021, 10 pages. [cited by applicant]
“Foreign Office Action”, CN Application No. 202080106238.6, Sep. 5, 2024, 18 pages. [cited by applicant]