Electronic integration circuit having offset and collected charge reduction circuitries and associated methods
An integrator having an offset evaluation circuit and a collected charge reduction circuitry and method for using the integrator. The integrator includes an amplifier, operable to amplify an input signal, an integration capacitor for collecting charge indicative of a level of the input signal and an offset capacitor. The offset evaluation circuit is operable to charge the offset capacitor with charge corresponding to an offset voltage of the amplifier and the collected charge reduction circuitry is operable to collect charge resulting from disconnection of the offset evaluation circuit, thereby reducing an amount of charge and associated noise input to the amplifier.
1. An integrator, comprising:
an amplifier operable to amplify an input signal;
an integration capacitor for collecting charge indicative of a level of the input signal;
an offset capacitor;
an offset evaluation circuit operable to charge the offset capacitor with charge corresponding to an offset voltage of the amplifier; and
a collected charge reduction circuitry operable to collect charge resulting from disconnection of the offset evaluation circuit,
wherein the input signal is coupled to a first input of the amplifier, wherein a reference signal is provided to a second input of the amplifier, and wherein the integration capacitor is coupled between an output of the amplifier and via the offset capacitor to the first input of the amplifier.
2. The integrator of claim 1 , wherein the input signal is provided by a source comprising at least one photodiode, operable to generate electric charge in response to light impinging on the at least one photodiode.
3. The integrator of claim 1 , wherein the offset capacitor is coupled between the first input of the amplifier and a reference voltage source.
4. The integrator of claim 1 , wherein the offset evaluation circuit is coupled between the output of the amplifier and the first input of the amplifier and is operable to selectively couple a first terminal of the offset capacitor to the output of the amplifier while a second terminal of the offset capacitor is coupled to the reference voltage source.
5. The integrator of claim 1 , wherein the collected charge reduction circuitry is coupled between the output of the amplifier and the first input of the amplifier.
6. The integrator of claim 1 , wherein the collected charge reduction circuitry comprises at least one capacitor.
7. The integrator of claim 1 , wherein the collected charge reduction circuitry is connected to the integrator via a switch.
8. The integrator of claim 7 , wherein the integration capacitor is connected between the switch and the first input of the amplifier and wherein the offset capacitor is connected between the switch and a dedicated reference signal.
9. A method, comprising:
connecting an offset evaluation circuit to charge an offset capacitor with a first charge corresponding to an offset voltage of an amplifier;
connecting a collected charge reduction circuitry between an output of the amplifier and a first input of the amplifier;
disconnecting the offset evaluation circuit;
by the collected charge reduction circuitry, collecting a second charge resulting from disconnection of the offset evaluation circuit; and
by an integration capacitor coupled between the output of the amplifier and via the offset capacitor to the first input of the amplifier, collecting a third charge indicative of a level of an input signal input to the amplifier, thereby reducing an amount of charge and associated noise input to the amplifier.
10. The method of claim 9 , wherein the connecting an offset evaluation circuit comprises connecting the offset evaluation circuit between the output of the amplifier and the first input of the amplifier, thereby coupling a first terminal of the offset capacitor to the output of the amplifier while a second terminal of the offset capacitor is coupled to a reference voltage source.
11. The method of claim 9 , wherein the input signal is coupled to the first input of the amplifier and wherein a reference signal is provided to a second input of the amplifier.
12. The method of claim 9 , wherein the offset capacitor is coupled between the first input of the amplifier and a reference voltage source.
13. The method of claim 9 , wherein the collected charge reduction circuitry comprises at least one capacitor.
14. The method of claim 9 , wherein the collected charge reduction circuitry is connected to the integrator via a switch.
15. The method of claim 14 , wherein the integration capacitor is connected between the switch and the first input of the amplifier and wherein the offset capacitor is connected between the switch and a dedicated reference signal.
16. The method of claim 9 , wherein the input signal is provided by a source comprising at least one photodiode, operable to generate electric charge in response to light impinging on the at least one photodiode.
17. An integrator, comprising:
an amplifier operable to amplify an input signal;
an integration capacitor for collecting charge indicative of a level of the input signal, wherein the input signal is coupled to a first input of the amplifier, and wherein a reference signal is provided to a second input of the amplifier;
an offset capacitor;
an offset evaluation circuit operable to charge the offset capacitor with charge corresponding to an offset voltage of the amplifier, wherein the offset evaluation circuit is coupled between the output of the amplifier and the first input of the amplifier and is operable to selectively couple a first terminal of the offset capacitor to the output of the amplifier while a second terminal of the offset capacitor is coupled to a reference voltage source; and
a collected charge reduction circuitry operable to collect charge resulting from disconnection of the offset evaluation circuit.
18. The integrator of claim 17 , wherein the input signal is provided by a source comprising at least one photodiode, operable to generate electric charge in response to light impinging on the at least one photodiode.
19. The integrator of claim 17 , wherein the collected charge reduction circuitry is connected to the integrator via a switch.