Substrate for carrying wafer
The present disclosure is to provide a wafer carrier substrate for carrying a wafer on which a plurality of chips is formed, elements to be measured being built in the plurality of chips. The wafer carrier substrate includes: a vacuuming hole for vacuuming of the wafer placed on the wafer carrier substrate; a wafer alignment guide for determining a predetermined position of the wafer placed on the wafer carrier substrate; and a mark for determining a probe contact position. It is possible to recognize a specific shot, without any additional processing of the semiconductor wafer.
1 . A wafer carrier substrate for carrying a wafer on which a plurality of chips is formed, an element to be measured being formed in the plurality of chips,
the wafer carrier substrate comprising:
a vacuuming hole for vacuuming of the wafer placed on the wafer carrier substrate;
a wafer alignment guide that determines a predetermined position of the wafer placed on the wafer carrier substrate; and
a mark that determines a probe contact position;
wherein the mark that determines the probe contact position enables identification of each line in a grid-like pattern on the wafer carrier substrate.
2 . The wafer carrier substrate according to claim 1 , further comprising two or more marks that determine the probe contact position.
3 . The wafer carrier substrate according to claim 1 , wherein a size of the mark is 100 μm or greater and 1 mm or shorter in both length and width, the mark determining the probe contact position.
4 . The wafer carrier substrate according to claim 1 , wherein the wafer alignment guide is a protruding portion with respect to the wafer carrier substrate.
5 . The wafer carrier substrate according to claim 1 , wherein the vacuuming hole functions as the wafer alignment guide.
6 . The wafer carrier substrate according to claim 1 , wherein the wafer carrier substrate is formed with a material that transmits infrared light.
7 . A wafer carrier substrate for carrying a wafer on which a plurality of chips is formed, an element to be measured being formed in the plurality of chips,
the wafer carrier substrate comprising:
a vacuuming hole for vacuuming of the wafer placed on the wafer carrier substrate;
a wafer alignment guide that determines a predetermined position of the wafer placed on the wafer carrier substrate; and
a mark that determines a probe contact position;
wherein the mark that determines the probe contact position is each line in a grid-like pattern on the wafer carrier substrate, and at least some of the respective lines are drawn by lines of types distinguishable from one another.
8 . The wafer carrier substrate according to claim 7 , further comprising two or more marks that determine the probe contact position.
9 . The wafer carrier substrate according to claim 7 , wherein a size of the mark is 100 μm or greater and 1 mm or shorter in both length and width, the mark determining the probe contact position.
10 . The wafer carrier substrate according to claim 7 , wherein the wafer alignment guide is a protruding portion with respect to the wafer carrier substrate.
11 . The wafer carrier substrate according to claim 7 , wherein the vacuuming hole functions as the wafer alignment guide.
12 . The wafer carrier substrate according to claim 7 , wherein the wafer carrier substrate is formed with a material that transmits infrared light.