Display paneland display device
A display panel includes a display area (AA), an OLED, and a pixel drive circuit. The display panel includes: a base substrate, first and second power lines, and a common electrode layer. The first and second power lines are located in the display area, the orthographic projection of the first power line is extended along the first direction, and the orthographic projection of the second power line is extended along the second direction, and the second direction is intersected with the first direction, at least a part of the second power line is connected to at least a part of the first power line through a via hole. The common electrode layer is located on one side of the base substrate, the common electrode layer is used to form the second electrode of the OLED, and the common electrode layer is connected to the first and second power lines.
1. A display panel, wherein the display panel comprises a display area, a light emitting unit located in the display area, and a pixel driving circuit for driving the light emitting unit, the pixel driving circuit is connected to a first electrode of the light emitting unit, and the display panel further comprises:
a base substrate;
a first power line, disposed in the display area of the display panel, wherein an orthographic projection of the first power line on the base substrate is extended along a first direction;
a second power line, disposed in the display area of the display panel, wherein an orthographic projection of the second power line on the base substrate is extended along a second direction, the second direction intersects the first direction, and at least a part of the second power line is connected to at least a part of the first power line through a via hole; and
a common electrode layer disposed at a side of the base substrate, wherein the common electrode layer is used to form a second electrode of the light emitting unit, and the common electrode layer is connected to the first power line and the second power line.
2. The display panel according to claim 1 , wherein both ends of the first power line are respectively connected to the common electrode layer, and both ends of the second power line are respectively connected to the common electrode layer.
3. The display panel according to claim 1 , wherein the pixel driving circuit comprises a driving transistor and a seventh transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit;
the display panel further comprises:
a first active layer, disposed between the base substrate and the common electrode layer, the first active layer comprises a third active part and a seventh active part, and the third active part is used for forming a channel region of the driving transistor, and the seventh active part is used for forming a channel region of the seventh transistor;
the orthographic projection of the second power line on the base substrate is at least partly overlapped with an orthographic projection of third active part on the base substrate, and the orthographic projection of the second power line on the base substrate is at least partly overlapped with an orthographic projection of seventh active part on the base substrate.
4. The display panel according to claim 1 , wherein the pixel driving circuit comprises an N-type transistor and a P-type transistor, and the display panel further comprises:
a first active layer, disposed between the base substrate and the common electrode layer, wherein a part of the first active layer is used to form a channel region of the P-type transistor;
a second active layer, disposed between the base substrate and the common electrode layer, wherein a part of the second active layer is used to form a channel region of the N-type transistor; and
a third conductive layer, disposed between the second active layer and the common electrode layer, wherein a part of the third conductive layer is used to form a top gate electrode of the N-type transistor;
wherein, at least part of the first power line is located at the third conductive layer.
5. The display panel according to claim 1 , wherein the pixel driving circuit comprises a driving transistor and a fifth transistor, a first electrode of the fifth transistor is connected to a third power line, and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor,
wherein the display panel further comprises:
a fifth conductive layer, disposed between the base substrate and the common electrode layer, the fifth conductive layer including the third power line;
wherein at least part of the second power line is located at the fifth conductive layer.
6. The display panel according to claim 5 , wherein the pixel driving circuit further comprises a fourth transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;
the fifth conductive layer further comprises the data line;
wherein, an orthographic projection of the data line on the base substrate and an orthographic projection of the third power line on the base substrate are extended along the second direction, and in a same column of pixel driving circuit, the orthographic projection on the base substrate, of the second power line at the fifth conductive layer, is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the third power line on the base substrate.
7. The display panel according to claim 1 , wherein the display panel further comprises:
a third conductive layer, disposed between the base substrate and the common electrode layer, wherein the first power line is located at the third conductive layer;
a fourth conductive layer, disposed between the third conductive layer and the common electrode layer, wherein the fourth conductive layer comprises a seventh bridging part; and
a fifth conductive layer, disposed between the fourth conductive layer and the common electrode layer, wherein the second power line is located at the fifth conductive layer;
wherein, an orthographic projection of the seventh bridging part on the base substrate is at least partially overlapped with an orthographic projection of the first power line on the base substrate, the orthographic projection of the seventh bridging part on the base substrate is at least partially overlapped with an orthographic projection of the second power line on the base substrate, and the seventh bridging part is respectively connected to the first power line and the second power line through via holes.
8. The display panel according to claim 7 , wherein the pixel driving circuit comprises: a driving transistor, a sixth transistor, and a seventh transistor, a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit;
wherein the display panel further comprises:
a first active layer, disposed between the base substrate and the third conductive layer, the first active layer comprises a sixth active part, a seventh active part, and a tenth active part, the sixth active part is used to form a channel region of the sixth transistor, the seventh active part is used to form a channel region of the seventh transistor, and the tenth active part is connected between the sixth active part and the seventh active part;
an orthographic projection of the seventh bridging part on the base substrate is at least partially overlap with an orthographic projection of the tenth active part on the base substrate.
9. The display panel according to claim 1 , wherein the first direction is a row direction, and the second direction is a column direction, the display panel comprises a plurality of repeating units distributed along the row and column directions, each repeating unit comprises a first pixel driving circuit and a second pixel driving circuit distributed along the row direction, and the first pixel driving circuit and the second pixel driving circuit are mirror-symmetrically disposed;
the pixel driving circuit comprises a driving transistor and a capacitor, a first electrode of the capacitor is connected to a gate electrode of the driving transistor, a second electrode of the capacitor is connected to a third power line, and the display panel further comprises:
a second conductive layer, disposed between the base substrate and the common electrode layer, wherein the second conductive layer comprises: a first conductive part, and the first conductive part is used to form the second electrode of the capacitor; and
a fifth conductive layer, disposed between the second conductive layer and the common electrode layer, the fifth conductive layer comprises the third power line, and each column of the pixel driving circuit is correspondingly provided with the third power line, and the third power line comprises: a first extension part, a second extension part, and a third extension part, and the second extension part is connected between the first extension part and the third extension part;
a size in the row direction, of an orthographic projection of the second extension part on the base substrate, is greater than a size in the row direction, of an orthographic projection of the first extension part on the base substrate, and the size in the row direction, of the orthographic projection of the second extension part on the base substrate, is greater than a size in the row direction, of an orthographic projection of the third extension part on the base substrate;
wherein, in a same repeating unit, the second extension parts in two adjacent third power lines are connected, and in the repeating units adjacent in the row direction, two adjacent first conductive parts are connected.
10. The display panel according to claim 1 , wherein the pixel driving circuit comprises a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor, and a first electrode of the fourth transistor connected to a data line, a second electrode of the fourth transistor is connected to a first electrode of the driving transistor, a first electrode of the fifth transistor is connected to a third power line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor, a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the seventh transistor is connected to a second electrode of the sixth transistor, and a first electrode of the seventh transistor is connected to a second initial signal line, a first electrode of the capacitor is connected to a gate electrode of the driving transistor, and a second electrode of the capacitor is connected to the third power line;
the display panel further comprises:
a first active layer, disposed between the base substrate and the common electrode layer, wherein the first active layer comprises:
a third active part, used to form a channel region of the driving transistor;
a fourth active part, used to form a channel region of the fourth transistor;
a fifth active part, used to form a channel region of the fifth transistor;
a sixth active part, used to form a channel region of the sixth transistor; and
a seventh active part, used to form a channel region of the seventh transistor;
a first conductive layer, disposed between the first active layer and the common electrode layer, wherein the first conductive layer comprises:
a second gate line, an orthographic projection of the second gate line on the base substrate is extended along the first direction and covers an orthographic projection of the fourth active part on the base substrate, a part of the second gate line is used to form a gate electrode of the fourth transistor;
an enable signal line, an orthographic projection of the enable signal line on the base substrate is extended along the first direction and covers an orthographic projection of the fifth active part on the base substrate and an orthographic projection of the sixth active part on the base substrate, a part of the enable signal line is used to form a gate electrode of the sixth transistor, and another part of the enable signal line is used to form a gate electrode of the fifth transistor;
a second reset signal line, an orthographic projection of the second reset signal line on the base substrate is extended along the first direction and covers an orthographic projection of the seventh active part on the base substrate, and a part of the second reset signal line is used to form a gate electrode of the seventh transistor; and
a second conductive part, an orthographic projection of the second conductive part on the base substrate covers an orthographic projection of the third active part on the base substrate, and the second conductive part is used to form the gate electrode of the driving transistor and the first electrode of the capacitor;
wherein, in a same pixel driving circuit, the orthographic projection of the second conductive part on the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the enable signal line on the base substrate; and
wherein an orthographic projection of the second reset signal line on the base substrate is located at a side of the orthographic projection of the enable signal line on the base substrate away from the orthographic projection of the second conductive part.
11. The display panel according to claim 10 , wherein the second gate line in a current row of pixel driving circuit is multiplexed as the second reset signal line in a previous row of pixel driving circuit.
12. The display panel according to claim 10 , wherein the pixel driving circuit further comprises a first transistor and a second transistor, a first electrode of the first transistor is connected to the gate electrode of the driving transistor, a second electrode of the first transistor is connected to a first initial signal line, a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor, wherein the display panel further comprises:
a second active layer, disposed between the first conductive layer and the common electrode layer, the second active layer comprising:
a first active part, used to form a channel region of the first transistor; and
a second active part, used to form a channel region of the second transistor;
a third conductive layer, disposed between the second active layer and the common electrode layer, the third conductive layer comprising:
a first reset signal line, an orthographic projection of the first reset signal line on the base substrate covers an orthographic projection of the first active part on the base substrate, and a part of the first reset signal line is used to form a top gate electrode of the first transistor; and
a first gate line, an orthographic projection of the first gate line on the base substrate covers an orthographic projection of the second active part on the base substrate, and a part of the first gate line is used to form a top gate electrode of the second transistor; and
a fifth conductive layer, disposed between the third conductive layer and the common electrode layer, wherein the fifth conductive layer comprises the third power line, and an orthographic projection of the third power line on the base substrate is overlapped with the orthographic projection of the first active part on the base substrate and the orthographic projection of the second active part on the base substrate;
in a same pixel driving circuit, the orthographic projection of the first gate line on the base substrate is located between the orthographic projection of the second conductive part on the base substrate and the orthographic projection of the second gate line on the base substrate, and the orthographic projection of the first reset signal line on the base substrate is located at a side of the orthographic projection of the second conductive part on the base substrate away from the orthographic projection of the second conductive part on the base substrate.
13. The display panel according to claim 12 , wherein the display panel further comprises a second conductive layer disposed between the first conductive layer and the second active layer, and the second conductive layer comprises:
a first initial signal line, an orthographic projection of the first initial signal line on the base substrate is located at a side of the orthographic projection of the first reset signal line on the base substrate away from the orthographic projection of the second conductive part on the base substrate;
a third reset signal line, connected to the first reset signal line through a via hole, and an orthographic projection of the third reset signal line on the base substrate covers the orthographic projection of the first active part on the base substrate, and a part of the third reset signal line is used to form a bottom gate electrode of the first transistor; and
a third gate line, an orthographic projection of the third gate line on the base substrate covers the orthographic projection of the second active part on the base substrate, and a part of the third gate line is used to form a bottom gate electrode of the second transistor.
14. The display panel according to claim 12 , wherein the first transistor and the second transistor are N-type transistors; and
the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are P-type transistors.
15. The display panel according to claim 10 , wherein the display panel further comprises:
a third conductive layer, disposed between the first conductive layer and the common electrode layer;
at least a part of the first power line is located at the third conductive layer, and the orthographic projection on the base substrate, of the first power line at the third conductive layer, is located between the orthographic projection of the second conductive part on the base substrate and the orthographic projection of the second reset signal line on the base substrate, and the orthographic projection on the base substrate, of the first power line at the third conductive layer, is at least partially overlapped with the orthographic projection of the enable signal line on the base substrate.
16. The display panel according to claim 15 , wherein an area of the orthographic projection on the base substrate, of the first power line at the third conductive layer, is S1; and
an overlapping area between the orthographic projection of the enable signal line on the base substrate and the orthographic projection on the base substrate, of the first power line at the third conductive layer, is S2,
wherein S2/S1 is greater than or equal to 80%.
17. The display panel according to claim 1 , wherein the pixel driving circuit comprises a driving transistor and a seventh transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light emitting unit;
wherein the display panel further comprises:
a fourth conductive layer, disposed between the base substrate and the common electrode layer, wherein the fourth conductive layer comprises a fourth bridging part, and the fourth bridging part is connected to a gate electrode of the driving transistor through a via hole;
wherein the second initial signal line is located at the fourth conductive layer.
18. The display panel according to claim 1 , wherein the display area comprises a fan-out area, and a normal display area;
a plurality of the first power lines comprise a first sub-power line, two first cutouts located in the fan-out area are formed on the first sub-power line, and the first sub-power line comprises a first sub-power line segment located between the two first cutouts;
a plurality of the second power lines comprise a second sub-power line, second cutouts located in the fan-out area are formed on the second sub-power line, the second sub-power line comprises a second sub-power line segment spaced by the second cutouts, and the second sub-power line segment is located in the fan-out area;
the display panel further comprises a plurality of data lines, orthographic projections of the data lines on the base substrate are extended along the second direction, and the plurality of data lines comprise a first data line;
wherein, the first data line is connected to the first sub-power line segment, and the first sub-power line segment is connected to the second sub-power line segment.
19. The display panel according to claim 1 , wherein the display panel further comprises:
a first signal line, disposed corresponding to a row of the pixel driving circuit, wherein an orthographic projection of the first signal line on the base substrate is extended along the first direction; and
a second signal line, disposed corresponding to a column of the pixel driving circuit, wherein an orthographic projection of the second signal line on the base substrate is extended along the second direction;
wherein the display panel further comprises a dummy pixel row and a dummy pixel column in the display area, wherein the first signal line in the dummy pixel row is multiplexed as the first power line, and the second signal line in the dummy pixel columns is multiplexed as the second power line.
20. A display device, comprising a display panel, wherein the display panel comprises:
a display area, a light emitting unit located in the display area, and a pixel driving circuit for driving the light emitting unit, the pixel driving circuit is connected to a first electrode of the light emitting unit, and the display panel further comprises:
a base substrate;
a first power line, disposed in the display area of the display panel, wherein an orthographic projection of the first power line on the base substrate is extended along a first direction;
a second power line, disposed in the display area of the display panel, wherein an orthographic projection of the second power line on the base substrate is extended along a second direction, the second direction intersects the first direction, and at least a part of the second power line is connected to at least a part of the first power line through a via hole; and
a common electrode layer disposed at a side of the base substrate, wherein the common electrode layer is used to form a second electrode of the light emitting unit, and the common electrode layer is connected to the first power line and the second power line.