Gate drive circuit, gate drive device, high-frequency power supply device, and system
A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate includes: a first terminal to which a gate control signal is input; a gate signal line connecting the first terminal and the first gate; a resistance element inserted in the gate signal line; a capacitance element connected in parallel with the resistance element; a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period.
1. A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate, the gate drive circuit comprising:
a first terminal to which a gate control signal is input;
a gate signal line connecting the first terminal and the first gate;
a resistance element inserted in the gate signal line;
a capacitance element connected in parallel with the resistance element;
a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and
a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period; and
a diode connected in parallel with the resistance element and including an anode connected to the first gate.
2. The gate drive circuit according to claim 1 ,
wherein the clamp circuit includes:
a first transistor switch connected between the first gate and the first source; and
a second transistor switch connected in parallel with the first transistor switch.
3. The gate drive circuit according to claim 2 , comprising:
an inverter that inverts a signal input to a gate of one of the first transistor switch and the second transistor switch and outputs the signal inverted to a gate of an other one of the first transistor switch and the second transistor switch,
wherein a channel of the first transistor switch and a channel of the second transistor switch differ in polarity.
4. A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate, the gate drive circuit comprising:
a first terminal to which a gate control signal is input;
a gate signal line connecting the first terminal and the first gate;
a resistance element inserted in the gate signal line;
a capacitance element connected in parallel with the resistance element;
a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and
a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period,
wherein the clamp control circuit includes:
a delay circuit that causes a delay of the gate control signal from the first terminal; and
a logic circuit that generates a timing signal indicating a timing of the off period of the switching element based on a logical AND or logical OR of the gate control signal before the delay and the gate control signal after the delay, and
the clamp circuit performs the clamp operation depending on the timing signal.
5. The gate drive circuit according to claim 4 ,
wherein an amount of the delay by the delay circuit is variable.
6. The gate drive circuit according to claim 4 ,
wherein the logic circuit receives input of an output state signal indicating a state of output power by switching of the switching element, and prohibits the clamp operation of the clamp circuit depending on the output state signal.
7. A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate, the gate drive circuit comprising:
a first terminal to which a gate control signal is input;
a gate signal line connecting the first terminal and the first gate;
a resistance element inserted in the gate signal line;
a capacitance element connected in parallel with the resistance element;
a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and
a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period,
wherein the clamp control circuit prohibits the clamp operation of the clamp circuit depending on an output state signal indicating a state of output power by switching of the switching element.
8. The gate drive circuit according to claim 6 ,
wherein the output state signal is based on at least one of information indicating reflected-wave power of the output power or information indicating traveling-wave power of the output power.
9. The gate drive circuit according to claim 6 , comprising:
a test circuit that prohibits the clamp operation by forcing the output state signal to a predetermined level, depending on a test signal input from outside.
10. The gate drive circuit according to claim 1 ,
wherein a distance between (i) a connection point of the clamp circuit and the gate signal line and (ii) the first gate in the gate signal line is less than a distance between the connection point and the resistance element in the gate signal line.
11. A gate drive device comprising:
the gate drive circuit according to claim 7 ; and
a state detection circuit that generates the output state signal,
wherein the state detection circuit:
detects at least one parameter indicating a state of output power from the switching element;
converts the at least one parameter into respective at least one binarized parameter indicating whether there is a possibility of false turn-on by threshold determination;
determines whether the at least one binarized parameter satisfies a predetermined condition; and
generates a determination result as the output state signal that is binary.
12. The gate drive device according to claim 11 ,
wherein the at least one parameter includes a parameter indicating traveling-wave power of the output power and a parameter indicating reflected-wave power of the output power.
13. The gate drive device according to claim 11 ,
wherein the at least one parameter includes a parameter indicating a voltage value of the output power, a parameter indicating a current value of the output power, and a parameter indicating a power value of the output power.
14. The gate drive device according to claim 11 ,
wherein the predetermined condition is an AND condition of one or more binarized parameters selected from the at least one binarized parameter.
15. A high-frequency power supply device comprising:
the gate drive device according to claim 11 ; and
the switching element.
16. The high-frequency power supply device according to claim 15 , comprising:
a positive power supply terminal;
a negative power supply terminal; and
a load inductor having a first end connected to the positive power supply terminal and a second end connected to the first drain,
wherein the first source and the negative power supply terminal are connected to each other.
17. The high-frequency power supply device according to claim 15 , comprising:
a positive power supply terminal;
a negative power supply terminal;
two switching elements, each of which is the switching element, connected in series between the positive power supply terminal and the negative power supply terminal; and
two gate drive circuits, each of which is the gate drive circuit, corresponding to the two switching elements,
wherein the two gate drive circuits exclusively cause the two switching elements to be conductive.
18. The high-frequency power supply device according to claim 15 , comprising:
a positive power supply terminal;
a negative power supply terminal;
a first leg including two switching elements, each of which is the switching element, connected in series between the positive power supply terminal and the negative power supply terminal;
a second leg including other two switching elements, each of which is the switching element, connected in series between the positive power supply terminal and the negative power supply terminal; and
four gate drive circuits, each of which is the gate drive circuit, corresponding to the two switching elements and the other two switching elements,
wherein the four gate drive circuits:
exclusively cause the two switching elements in the first leg to be conductive;
exclusively cause the other two switching elements in the second leg to be conductive;
simultaneously cause the switching element as a high side switch in the first leg and the switching element as a low side switch in the second leg to be conductive; and
simultaneously cause the switching element as a high side switch in the second leg and the switching element as a low side switch in the first leg to be conductive.
19. A system comprising:
the high-frequency power supply device according to claim 15 ; and
a load connected to the high-frequency power supply device.