Vector reading and writing method, vector register system, device, and medium
View Patent ↗The present disclosure discloses a method for vector reading-writing, a vector-register system, a device and a medium. When a vector-writing instruction is obtained, by using a vector-register controller, a to-be-written-vector address space is converted into a to-be-written-vector-register-file bit address, and, for a nonstandard vector, by using a nonstandard-vector converting unit, after the nonstandard vector is converted into a to-be-written nonstandard vector, and, subsequently, writing is performed, to realize the saving of vector data of any format. When a vector-reading instruction is obtained, by using the vector-register controller, according to the to-be-read width and the to-be-read length, after the to-be-read-vector address space is converted into a to-be-read-vector-register-file bit address, and, subsequently, reading is performed, to realize the reading of vector data of any format.
1. A method for vector reading-writing, applied to a predetermined vector-register system, comprising:
by a vector-register controller, obtaining a vector-operation instruction sent by a processor, wherein the vector-operation instruction comprises a vector-writing instruction and/or a vector-reading instruction;
when the vector-operation instruction is the vector-writing instruction, by the vector-register controller, converting a to-be-written-vector address space in the vector-writing instruction into a to-be-written-vector-register-file bit address;
by a nonstandard-vector converting unit, obtaining a to-be-written standard vector of first preset length and width sent by a vector processing unit, and when a received first converting instruction sent by the vector-register controller indicates that a valid vector in the to-be-written vector is a nonstandard vector, converting the to-be-written standard vector into a to-be-written nonstandard vector; and
by a vector-register file, obtaining the to-be-written-vector-register-file bit address, and storing the to-be-written nonstandard vector into the to-be-written-vector-register-file bit address; and
when the vector-operation instruction is the vector-reading instruction, according to a to-be-read width and a to-be-read length that correspond to the vector-reading instruction, by the vector-register controller, converting a to-be-read-vector address space in the vector-reading instruction into a to-be-read-vector-register-file bit address, wherein the to-be-read width is a standard width or a nonstandard width, and the to-be-read length is a standard length or a nonstandard length; and
by the vector-register file, obtaining the to-be-read-vector-register-file bit address, and outputting a to-be-read vector corresponding to the to-be-read-vector-register-file bit address.
2. The method for vector reading-writing according to claim 1 , wherein according to the to-be-read width and the to-be-read length that correspond to the vector-reading instruction, by the vector-register controller, converting the to-be-read-vector address space in the vector-reading instruction into the to-be-read-vector-register-file bit address comprises:
determining whether a vector-length-width register sends the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller; and
when the vector-length-width register sends the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller, according to the to-be-read-vector address space in the vector-reading instruction, the to-be-read length and the to-be-read width, determining the to-be-read-vector-register-file bit address.
3. The method for vector reading-writing according to claim 2 , wherein according to the to-be-read-vector address space in the vector-reading instruction, the to-be-read length and the to-be-read width, determining the to-be-read-vector-register-file bit address comprises:
regarding a product of the to-be-read length and the to-be-read width as a data-bit-address length of the to-be-read vector in the vector-register file; and
from a first register in the vector-register controller, determining a to-be-read head address of the to-be-read-vector address space in the vector-register file, and inputting the data-bit-address length and the to-be-read head address into a reading-data address line of the vector-register file, so that the vector-register file obtains the to-be-read-vector-register-file bit address.
4. The method for vector reading-writing according to claim 3 , wherein by the vector-register file, obtaining the to-be-read-vector-register-file bit address comprises:
by the reading-data address line of the vector-register file, obtaining the data-bit-address length, wherein a width of the reading-data address line is a data bit number that the vector-register file is capable of storing, to operate the vector-register file with a precision of a bit; and
by the reading-data address line of the vector-register file, obtaining the to-be-read head address, and shifting the data-bit-address length by a length of the to-be-read head address, to obtain the to-be-read-vector-register-file bit address, wherein the reading-data address line is controlled by a shift controller.
5. The method for vector reading-writing according to claim 2 , wherein after determining whether the vector-length-width register sends the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller, the method further comprises:
when the vector-length-width register does not send the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller, from a first register in the vector-register controller, determining a to-be-read head address of the to-be-read-vector address space in the vector-register file;
determining a vector length in a second register in the vector-register controller that corresponds to the to-be-read-vector address space as the to-be-read length, and determining a vector width in a third register in the vector-register controller that corresponds to the to-be-read-vector address space as the to-be-read width;
regarding a product of the to-be-read length and the to-be-read width as a data-bit-address length of the to-be-read vector in the vector-register file; and
inputting the data-bit-address length and the to-be-read head address into a reading-data address line of the vector-register file, so that the vector-register file obtains the to-be-read-vector-register-file bit address.
6. The method for vector reading-writing according to claim 1 , wherein after outputting the to-be-read vector corresponding to the to-be-read-vector-register-file bit address, the method further comprises:
by the nonstandard-vector converting unit, obtaining the to-be-read vector, and when a received second converting instruction sent by the vector-register controller indicates that the to-be-read vector is a nonstandard vector, converting the to-be-read vector into a standard vector of second preset length and width, and sending a to-be-read standard vector that is obtained by the conversion to the vector processing unit, wherein the second preset length and width refer to a length and a width of a predetermined inputted vector of the vector processing unit, and the standard vector refers to a vector whose length is a power of 2.
7. The method for vector reading-writing according to claim 6 , wherein when the received second converting instruction sent by the vector-register controller indicates that the to-be-read vector is the nonstandard vector, converting the to-be-read vector into the standard vector of second preset length and width comprises:
receiving the second converting instruction sent by the vector-register controller, wherein the second converting instruction contains a first actual length and a first actual width of the to-be-read vector; and
when the first actual length is not a power of 2, which indicates that the to-be-read vector is the nonstandard vector, reading the second preset length and width from the nonstandard-vector converting unit, supplementing a vector length of the to-be-read vector from the first actual length to a preset length of the second preset length and width, and supplementing a vector width of each of elements of the to-be-read vector from the first actual width to a preset width of the second preset length and width, to convert the to-be-read vector into a standard vector of the second preset length and width.
8. The method for vector reading-writing according to claim 1 ,
wherein vector elements in the vector-register file are continuously stored, and there is not a null bit between any two neighboring vector elements in a vector in the vector-register file.
9. A vector-register system, comprising:
a vector-register controller configured for obtaining a vector-operation instruction sent by a processor, wherein the vector-operation instruction comprises a vector-writing instruction and/or a vector-reading instruction;
wherein the vector-register controller is further configured for, when the vector-operation instruction is the vector-writing instruction, converting a to-be-written-vector address space in the vector-writing instruction into a to-be-written-vector-register-file bit address;
a nonstandard-vector converting unit configured for obtaining a to-be-written standard vector of first preset length and width sent by a vector processing unit, and when a received first converting instruction sent by the vector-register controller indicates that a valid vector in the to-be-written vector is a nonstandard vector, converting the to-be-written standard vector into a to-be-written nonstandard vector; and
a vector-register file configured for obtaining the to-be-written-vector-register-file bit address, and storing the to-be-written nonstandard vector into the to-be-written-vector-register-file bit address;
wherein the vector-register controller is further configured for, when the vector-operation instruction is the vector-reading instruction, according to a to-be-read width and a to-be-read length that correspond to the vector-reading instruction, converting a to-be-read-vector address space in the vector-reading instruction into a to-be-read-vector-register-file bit address, wherein the to-be-read width is a standard width or a nonstandard width, and the to-be-read length is a standard length or a nonstandard length; and
wherein the vector-register file is further configured for, by the vector-register file, obtaining the to-be-read-vector-register-file bit address, and outputting a to-be-read vector corresponding to the to-be-read-vector-register-file bit address.
10. An electronic device, wherein the electronic device comprises the vector-register system according to claim 9 .
11. A non-transitory computer-readable storage medium, wherein the computer-readable storage medium is configured to save a computer program, and the computer program, when executed by a processor, implements the method for vector reading-writing according to claim 1 .
12. The method for vector reading-writing according to claim 1 , wherein the first preset length and width are a length and a width of fixed standards.
13. The method for vector reading-writing according to claim 1 , wherein the first converting instruction contains a writing length and a writing width, and the writing length and the writing width are actual effective length and width in the to-be-written standard vector.
14. The method for vector reading-writing according to claim 1 , wherein the vector-register controller comprises a first controller, and the first controller is configured for storing the head address in a vector register of each vector.
15. The method for vector reading-writing according to claim 1 , wherein after, by the vector-register controller, converting the to-be-read-vector address space in the vector-reading instruction into the to-be-read-vector-register-file bit address, the method further comprises:
sending the to-be-read-vector-register-file bit address to the vector-register file by the vector-register controller, wherein the vector-register file is configured for registering vectors.
16. The method for vector reading-writing according to claim 5 , wherein the second register records a length of each vector in the vector-register file, and the third register records a width of each vector in the vector-register file.
17. The non-transitory computer-readable storage medium according to claim 11 , wherein according to the to-be-read width and the to-be-read length that correspond to the vector-reading instruction, by the vector-register controller, converting the to-be-read-vector address space in the vector-reading instruction into the to-be-read-vector-register-file bit address comprises:
determining whether a vector-length-width register sends the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller; and
when the vector-length-width register sends the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller, according to the to-be-read-vector address space in the vector-reading instruction, the to-be-read length and the to-be-read width, determining the to-be-read-vector-register-file bit address.
18. The non-transitory computer-readable storage medium according to claim 17 , wherein according to the to-be-read-vector address space in the vector-reading instruction, the to-be-read length and the to-be-read width, determining the to-be-read-vector-register-file bit address comprises:
regarding a product of the to-be-read length and the to-be-read width as a data-bit-address length of the to-be-read vector in the vector-register file; and
from a first register in the vector-register controller, determining a to-be-read head address of the to-be-read-vector address space in the vector-register file, and inputting the data-bit-address length and the to-be-read head address into a reading-data address line of the vector-register file, so that the vector-register file obtains the to-be-read-vector-register-file bit address.
19. The non-transitory computer-readable storage medium according to claim 18 , wherein by the vector-register file, obtaining the to-be-read-vector-register-file bit address comprises:
by the reading-data address line of the vector-register file, obtaining the data-bit-address length, wherein a width of the reading-data address line is a data bit number that the vector-register file is capable of storing, to operate the vector-register file with a precision of a bit; and
by the reading-data address line of the vector-register file, obtaining the to-be-read head address, and shifting the data-bit-address length by a length of the to-be-read head address, to obtain the to-be-read-vector-register-file bit address, wherein the reading-data address line is controlled by a shift controller.
20. The non-transitory computer-readable storage medium according to claim 17 , wherein after determining whether the vector-length-width register sends the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller, the method further comprises:
when the vector-length-width register does not send the to-be-read length and the to-be-read width that correspond to the vector-reading instruction to the vector-register controller, from a first register in the vector-register controller, determining a to-be-read head address of the to-be-read-vector address space in the vector-register file;
determining a vector length in a second register in the vector-register controller that corresponds to the to-be-read-vector address space as the to-be-read length, and determining a vector width in a third register in the vector-register controller that corresponds to the to-be-read-vector address space as the to-be-read width;
regarding a product of the to-be-read length and the to-be-read width as a data-bit-address length of the to-be-read vector in the vector-register file; and
inputting the data-bit-address length and the to-be-read head address into a reading-data address line of the vector-register file, so that the vector-register file obtains the to-be-read-vector-register-file bit address.