Semiconductor package
A semiconductor package according to an embodiment includes a first substrate layer; and a second substrate layer disposed on the first substrate layer, wherein the first substrate layer includes at least one first insulating layer; a first circuit pattern disposed on the first insulating layer; and a first via passing through the first insulating layer and connected to the first circuit pattern, wherein the second substrate layer includes a second insulating layer disposed on the first insulating layer; a second circuit pattern disposed on the second insulating layer; and a second via passing through the second insulating layer and connected to the second circuit pattern, wherein the first insulating layer and the second insulating layer include different insulating materials and wherein a width of the first via is different from a width of the second via.
1 . A circuit board comprising:
a first insulating layer;
a second insulating layer including a photocurable insulating material disposed on an upper surface of the first insulating layer, the second insulating layer made of a material different from the first insulating layer;
a first via electrode disposed to pass through at least a portion of the first insulating layer; and
a second via electrode disposed to pass through at least a portion of the second insulating layer and overlapping the first via electrode in a vertical direction,
wherein the first via electrode has a slope in which a horizontal width gradually increases along a vertical direction from an upper surface of the first via electrode to a lower surface of the first via electrode,
wherein the second via electrode has a slope in which a horizontal width gradually decreases along a vertical direction from an upper surface of the second via electrode to a lower surface of the second via electrode,
wherein the first via electrode has a greatest horizontal width at the lower surface of the first via electrode, and the second via electrode has a greatest horizontal width at the upper surface of the second via electrode, and
wherein a horizontal width of the lower surface of the first via electrode is different from a horizontal width of the upper surface of the second via electrode.
2 . The circuit board of claim 1 , wherein the horizontal width of the lower surface of the first via electrode is greater than the horizontal width of the upper surface of the second via electrode.
3 . The circuit board of claim 1 , further comprising:
a plurality of first circuit patterns disposed on a lower surface of the first insulating layer; and
a plurality of second circuit patterns disposed on an upper surface of the second insulating layer,
wherein a horizontal width of each of the plurality of first circuit patterns or a spacing between the plurality of first circuit patterns is different from a horizontal width of each of the plurality of second circuit patterns or a spacing between the plurality of second circuit patterns.
4 . The circuit board of claim 3 , wherein the horizontal width of each of the plurality of first circuit patterns or the spacing between the plurality of first circuit patterns is greater than the horizontal width of each of the plurality of second circuit patterns or the spacing between the plurality of second circuit patterns.
5 . The circuit board of claim 3 , wherein the first insulating layer includes a first-first insulating layer disposed below a lower surface of the second insulating layer, and a first-second insulating layer disposed below a lower surface of the first-first insulating layer,
wherein the second insulating layer includes a second-first insulating layer disposed on an upper surface of the first-first insulating layer, and a second-second insulating layer disposed on an upper surface of the second-first insulating layer,
wherein the first via electrode includes a first-first via electrode passing through at least a portion of the first-first insulating layer, and a first-second via electrode passing through at least a portion of the first-second insulating layer, and
wherein the second via electrode includes a second-first via electrode passing through at least a portion of the second-first insulating layer and a second-second via electrode passing through at least a portion of the second-second insulating layer.
6 . The circuit board of claim 5 , wherein a thickness of each of the first-first insulating layer and the first-second insulating layer is greater than a thickness of each of the second-first insulating layer and the second-second insulating layer.
7 . The circuit board of claim 5 , wherein a direction in which a slope of the first-first via electrode is inclined is the same as a direction in which a slope of the first-second via electrode is inclined, and
wherein a direction in which a slope of the second-first via electrode is inclined is the same as a direction in which a slope of the second-second via electrode is inclined and different from the direction in which the slopes of each of the first-first via electrode and the first-second via electrode are inclined.
8 . The circuit board of claim 5 , wherein a horizontal width of each lower surface of the first-first and first-second via electrodes is greater than a horizontal width of each upper surface of the second-first and second-second via electrodes,
wherein the horizontal width of the lower surface of the first-first via electrode is different from the horizontal width of the lower surface of the first-second via electrode, and
wherein the horizontal width of the upper surface of the second-first via electrode is different from the horizontal width of the upper surface of the second-second via electrode.
9 . The circuit board of claim 6 , wherein the first-second via electrode is disposed farther away from the second-first via electrode than the first-first via electrode, and
wherein the horizontal width of the lower surface of the first-second via electrode is greater than the horizontal width of the lower surface of the first-first via electrode.
10 . The circuit board of claim 6 , wherein the second-second via electrode is disposed farther away from the first-first via electrode than the second-first via electrode, and
wherein the horizontal width of the upper surface of the second-second via electrode is greater than the horizontal width of the upper surface of the second-first via electrode.
11 . The circuit board of claim 5 , wherein the first circuit pattern includes a first-first circuit pattern disposed on a lower surface of the first-first insulating layer and a first-second circuit pattern disposed on a lower surface of the first-second insulating layer, and
wherein the second circuit pattern includes a second-first circuit pattern disposed on an upper surface of the second-first insulating layer and a second-second circuit pattern disposed on an upper surface of the second-second insulating layer.
12 . The circuit board of claim 11 , wherein a horizontal width or spacing of at least one of the first-first circuit pattern and the first-second circuit pattern is greater than a horizontal width or spacing of at least one of the second-first circuit pattern and the second-second circuit pattern,
wherein the horizontal width or spacing of the first-first circuit pattern is different from the horizontal width or spacing of the first-second circuit pattern, and
wherein the horizontal width or spacing of the second-first circuit pattern is different from the horizontal width or spacing the second-second circuit pattern.
13 . The circuit board of claim 12 , wherein the first-second circuit pattern is disposed farther away from the second-first circuit pattern than the first-first circuit pattern, and
wherein the horizontal width or the spacing of the first-second circuit pattern is greater than the horizontal width or the spacing of the first-first circuit pattern.
14 . The circuit board of claim 13 , wherein the second-second circuit pattern is disposed farther away from the first-first circuit pattern than the second-first circuit pattern, and
wherein the horizontal width or the spacing of the second-second circuit pattern is smaller than the horizontal width or spacing of the second-first circuit pattern.
15 . The circuit board of claim 12 , wherein the second insulating layer further includes a second-third insulating layer disposed on an upper surface of the second-second insulating layer,
wherein the second circuit pattern further includes a second-third circuit pattern disposed on an upper surface of the second-third insulating layer,
wherein the second-second circuit pattern is disposed in a first recess provided at a lower surface of the second-second insulating layer, and
wherein the second-third circuit pattern is disposed in a second recess provided at upper surface of the second-third insulating layer.
16 . A semiconductor package comprising:
a first insulating layer;
a second insulating layer including a photocurable insulating material disposed on an upper surface of the first insulating layer, the second insulating layer made of a material different from the first insulating layer;
a first via electrode disposed to pass through at least a portion of the first insulating layer; and
a second via electrode disposed to pass through at least a portion of the second insulating layer and overlapping the first via electrode in a vertical direction;
a plurality of pads disposed on the second insulating layer and spaced apart in a horizontal direction; and
a semiconductor chip disposed on the plurality of pads,
wherein the first via electrode has a slope in which a horizontal width gradually increases along a vertical direction from an upper surface of the first via electrode to a lower surface of the first via electrode,
wherein the second via electrode has a slope in which a horizontal width gradually decreases along a vertical direction from an upper surface of the second via electrode to a lower surface of the second via electrode,
wherein the first via electrode has a greatest horizontal width at the lower surface of the first via electrode, and the second via electrode has a greatest horizontal width at the upper surface of the second via electrode, and
wherein a horizontal width of the lower surface of the first via electrode is different from a horizontal width of the upper surface of the second via electrode.
17 . The semiconductor package of claim 16 ,
wherein the horizontal width of the lower surface of the first via electrode is greater than the horizontal width of the upper surface of the second via electrode.
18 . The semiconductor package of claim 16 , wherein a plurality of semiconductor chips are mounted on the plurality of pads and spaced apart in the horizontal direction, and
wherein the plurality of semiconductor chips include at least two of a first application processor chip, a second application processor chip, and a memory chip.