System and methods for hardware voting-based clock control
The present disclosure provides computer-implemented methods, systems, and devices for controlling an external shared clock in a computing system with a plurality of system on a chips (SoCs). To do so, while a first SoC is in a low power mode, the second SoC receives a wake-up input that causes the second SoC to exit a low power mode. The second SoC asserts a clock request signal line to activate an external shared clock. The clock control system determines a state associated with the external shared clock, wherein the external shared clock is external to the first SoC. The clock control system, in accordance with a determination that the external shared clock is in an off state, transmits a signal to the external shared clock to cause the external shared clock to enter a startup state and begin producing a shared clock signal.
1 . A clock control system included in a first system on a chip (SoC) comprising:
a processor,
one or more input pins connected to one or more clock request signal lines controlled by one or more second SoCs;
a communication interface for communicating with an external shared clock that is external to the first SoC; and
one or more control circuits configured to:
determine based on a state of the one or more input pins that a respective clock request signal line controlled by at least one of the one or more second SoCs has been set to a predetermined high voltage;
determine a current state of the external shared clock; and
in accordance with a determination that the external shared clock is currently in an off state, transmit instructions, via the communication interface, to cause the external shared clock to enter a startup state and begin producing a shared clock signal.
2 . The clock control system of claim 1 , wherein the processor included in the first SoC is in a low power state when the clock control system determines that the respective clock request signal line controlled by the at least one of the one or more second SoCs has been set to the predetermined high voltage and does not leave the low power state in response to the respective clock request signal line controlled by the at least one of the one or more second SoCs being set to the predetermined high voltage.
3 . The clock control system of claim 1 , wherein the current state of the external shared clock is one of the off state, the startup state, and a stable signal production state.
4 . The clock control system of claim 3 , wherein the clock control system uses a state machine to track a state of the external shared clock.
5 . The clock control system of claim 3 , wherein the one or more control circuits are further configured to:
after transmitting instructions, via the communication interface, to cause the external shared clock to enter the startup state and begin producing the shared clock signal, update the current state of the external shared clock to the startup state.
6 . The clock control system of claim 3 , wherein the one or more control circuits are further configured to, after a predetermined period of time, update the current state of the external shared clock to the stable signal production state.
7 . The clock control system of claim 1 , wherein the first SoC and at least two second SoCs are included within a computing device.
8 . The clock control system of claim 1 , wherein the one or more control circuits are further configured to:
determine that the respective clock request signal line controlled by the at least one of the one or more second SoCs has been set to a predetermined low voltage;
determine whether at least one other clock request signal line is currently set to the predetermined high voltage; and
in response to a determination that no other clock request signal line is currently set to the predetermined high voltage, transmit instructions, via the communication interface, to cause the external shared clock to enter the off state and cease production of the shared clock signal.
9 . The clock control system of claim 8 , wherein the one or more control circuits are further configured to:
in response to a determination that the at least one other clock request signal line is currently set to the predetermined high voltage, direct the external shared clock to continue producing the shared clock signal.
10 . The clock control system of claim 7 , wherein the first SoC and the at least two second SoCs use the shared clock signal produced by the external shared clock.
11 . The clock control system of claim 1 , wherein the one or more input pins are general purpose input/output pins.
12 . A method for controlling an external shared clock in a computing system with a plurality of system on a chips (SoCs), the method comprising:
while a first SoC is in a low power mode:
asserting, by a second SoC, a clock request signal line to activate the external shared clock, wherein the clock request signal line is connected to an input pin of a clock control system within the first SoC;
determining, by the clock control system, a state associated with the external shared clock, wherein the external shared clock is external to the first SoC; and
in accordance with a determination that the external shared clock is in an off state, transmitting a signal to the external shared clock to cause the external shared clock to enter a startup state and begin producing a shared clock signal.