Granted Patent B2

US 12,301,225 · App. 18/291,056 · Granted May 13, 2025

Inventors: Min Jan Tsai (Richmond, CA); Emile M. Hoskinson (Vancouver, CA); Mark H. Volkmann (Burnaby, CA)

Assignee: 1372934 B.C. LTD.

H03K17/92

Abstract

Claims (34)

1. A quantum processor comprising:

a first current path comprising a capacitance, an inductance, and a first loop;

a Josephson structure interrupting the first loop, the Josephson structure comprising at least one Josephson junction;

a second current path extending from and electrically connected to the first current path at a first end and a second end, the second current path comprising:

a first node spaced from a second node;

a capacitor separating the first node and the second node; and

a voltage gain tuner, the voltage gain tuner being inductively coupled to the inductance of the first current path;

a flux bias line coupled to the voltage gain tuner; and

wherein the flux bias line controls the voltage gain tuner to vary a voltage ratio between the first node and the second node, thereby influencing the capacitance of the first current path.

2. The quantum processor of claim 1 , wherein the second current path is electrically connected in parallel with the first loop.

3. The quantum processor of claim 1 , wherein the second current path is electrically connected in series with the first loop.

4. The quantum processor of claim 1 , wherein the voltage gain tuner comprises a quantum flux parametron.

5. The quantum processor of claim 1 , wherein the first loop and the Josephson structure comprise a qubit.

6. The quantum processor of claim 1 , wherein the flux bias line receives a programming signal.

7. The quantum processor of claim 1 , wherein the first current path and the second current path comprise a superconducting material.

8. The quantum processor of claim 7 , wherein the superconducting material comprises at least one of: Nb, Al, WSi, MON, NbN, NbTiN, and TiN.

9. A method of tuning an effective capacitance of a device in a quantum processor, the method performed by a processor in communication with the quantum processor and comprising:

determining a target capacitance of the device;

measuring the effective capacitance of the device;

computing a difference between the target capacitance and the effective capacitance; and

in response to the difference being greater than a threshold value:

introducing a flux bias to a voltage gain tuner, the voltage gain tuner inductively coupled to an inductance of the device and positioned on a current path electrically connected at a first end and a second end to the device, such that a voltage ratio between a first node on the current path and a second node on the current path separated from the first node on the current path by a capacitor is varied; and

controlling the flux bias to reduce the difference between the target capacitance and the effective capacitance.

10. The method of claim 9 , wherein introducing the flux bias to the voltage gain tuner comprises applying a programming signal through a flux bias line.

11. The method of claim 9 , wherein determining the target capacitance of the device comprises determining the target capacitance of a qubit.

12. The method of claim 11 , wherein determining the target capacitance of the qubit comprises retrieving a fabrication target capacitance shared by a plurality of qubits including the qubit.

13. The method of claim 9 , wherein determining the target capacitance of the device comprises determining the target capacitance of a coupler.

14. The method of claim 13 , wherein determining the target capacitance of the coupler comprises retrieving a fabrication target capacitance shared by a plurality of couplers including the coupler.

15. A method of tuning qubit capacitance, the method being performed by one or more processors, the one or more processors communicatively coupled to a quantum processor, the method comprising:

causing the quantum processor to evolve from an initial state to a final state over a time interval, the quantum processor comprising a qubit, the qubit comprising a capacitance;

introducing a flux bias to a voltage gain tuner, the voltage gain tuner inductively coupled to the qubit and positioned on a current path electrically connected to the qubit at a first end and a second end, such that a voltage ratio between a first node on the current path and a second node on the current path separated from the first node on the current path by a capacitor is varied; and

controlling the flux bias according to a time dependent signal to vary the capacitance of the qubit over the time interval.

16. The method of claim 15 , wherein the quantum processor comprises a plurality of qubits, and wherein controlling the flux bias according to a time dependent signal comprises controlling the flux bias of a plurality of voltage gain tuners to vary the capacitance of the plurality of qubits over the time interval.

17. The method of claim 15 , wherein causing the quantum processor to evolve from an initial state to a final state over a time interval comprises causing the quantum processor to perform quantum annealing.

Assignments (4)

Continuity (2)

References Cited (277)

Cited By (1)

US 12,632,761