Semiconductor integrated circuit device with first memory cell and third memory cell, and manufacturing method therefor
A semiconductor integrated circuit device includes a resistive layer having a trench-like structure with an upward opening, a first electrode located on an outer side of the resistive layer, and a second electrode located on an inner side of the resistive layer; the first electrode and the second electrode are opposite to each other on two sides of a sidewall of the resistive layer; and the resistive layer, the first electrode and the second electrode form a first memory cell. A manufacturing method includes forming a first electrode on a substrate, the substrate including a first via connected with a first metal layer; etching a recess in the first electrode at a position staggered from the first via and forming a resistive layer in the recess; and forming a second electrode in the opening of the resistive layer to obtain a first memory cell.
1 . A semiconductor integrated circuit device, comprising:
a resistive layer having a trench-like structure with an upward opening; and
a first electrode located on an outer side of the resistive layer, and a second electrode located on an inner side of the resistive layer; wherein the first electrode and the second electrode are opposite to each other on two sides of a sidewall of the resistive layer;
wherein the resistive layer, the first electrode and the second electrode form a first memory cell;
further comprising:
a via located below the first electrode;
a first metal layer connected to the first electrode through the via; and
a second metal layer connected to the second electrode; and
further comprising: a third memory cell having a same structure as the first memory cell, wherein a first electrode of the third memory cell is connected with the first metal layer through a via below.
2 . The semiconductor integrated circuit device according to claim 1 , further comprising:
a second memory cell having a same structure as the first memory cell, wherein a first electrode of the second memory cell is connected with the first metal layer through a via below, a second electrode of the second memory cell is connected with the second metal layer, and a partition is formed between the first memory cell and the second memory cell.
3 . The semiconductor integrated circuit device according to claim 1 , wherein a second electrode of the third memory cell is connected with a third metal layer through a second metal layer and a via above, thereby forming a 1T2R structure.
4 . A manufacturing method of a semiconductor integrated circuit device, comprising:
forming a first electrode on a substrate, the substrate comprising a first via connected with a first metal layer;
etching a recess in the first electrode at a position staggered from the first via, and forming a resistive layer in the recess, such that the resistive layer has a trench-like structure with an upward opening; and
forming a second electrode in the opening of the resistive layer to obtain a first memory cell;
further comprising:
manufacturing a third memory cell while manufacturing the first memory cell, such that a first electrode of the third memory cell is connected with the first metal layer through a via below.
5 . The manufacturing method according to claim 4 , further comprising:
forming a second metal layer on the second electrode and connecting the second metal layer with the second electrode of the first memory cell.
6 . The manufacturing method according to claim 5 , further comprising:
manufacturing a second memory cell while manufacturing the first memory cell, such that a first electrode of the second memory cell is connected with the first metal layer through a via below, and a second electrode of the second memory cell is connected with the second metal layer; and
forming a partition between the first memory cell and the second memory cell.
7 . The manufacturing method according to claim 4 , further comprising:
forming a second metal layer, a via and a third metal layer above a second electrode of the third memory cell, such that the second electrode of the third memory cell is connected with the third metal layer through the second metal layer and the via above, thereby forming a 1T2R structure.