Fast-transient buffer
A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.
1. A fast-transient buffer, comprising:
a flipped voltage follower and a bias circuit coupled to the flipped voltage follower, wherein the flipped voltage follower is coupled between an input terminal and an output terminal of the fast-transient buffer; and
a first MOS transistor, coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer, wherein the first MOS transistor regulates an output voltage of the output terminal of the fast-transient buffer, in an opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower;
wherein:
the first MOS transistor has a drain terminal coupled to the output terminal of the fast-transient buffer,
the flipped voltage follower has a second MOS transistor, a third MOS transistor, and a fourth MOS transistor;
the second MOS transistor has a gate terminal coupled to the input terminal of the fast-transient buffer, a source terminal coupled to the output terminal of the fast-transient buffer, and a drain terminal coupled to a gate terminal of the first MOS transistor;
the third MOS transistor has a drain terminal coupled to the source terminal of the second MOS transistor;
the fourth MOS transistor has a source terminal coupled to the drain terminal of the second MOS transistor, and a drain terminal coupled to the gate terminal of the third MOS transistor; and
the bias circuit is coupled to a gate terminal of the fourth MOS transistor to further bias the first MOS transistor through the fourth MOS transistor.
2. The fast-transient buffer as claimed in claim 1 , wherein:
the first MOS transistor is a PMOS, and the source terminal of the first MOS transistor is coupled to a power terminal;
the second MOS transistor is an NMOS;
the third MOS transistor is an NMOS, and a source terminal of the third MOS transistor is coupled to a ground terminal; and
the fourth MOS transistor is a PMOS.
3. The fast-transient buffer as claimed in claim 2 , wherein the flipped voltage follower further comprises:
a first current source, coupled to a connection terminal between the gate terminal of the first MOS transistor, the drain terminal of the second MOS transistor and the source terminal of the fourth MOS transistor to provide a first current; and
a second current source, coupled to a connection terminal between the drain terminal of the fourth MOS transistor and the gate terminal of the third MOS transistor to sink a second current.
4. The fast-transient buffer as claimed in claim 3 , wherein the bias circuit comprises:
a fifth MOS transistor that is a diode-connected PMOS; and
a sixth MOS transistor that is a diode-connected PMOS;
wherein the fifth MOS transistor and the sixth MOS transistor are connected in series between the power terminal and the gate terminal of the fourth MOS transistor.
5. The fast-transient buffer as claimed in claim 4 , wherein the bias circuit further comprises:
a third current source, coupled to a connection terminal between a drain terminal of the sixth transistor and the gate terminal of the fourth transistor to sink a third current.
6. The fast-transient buffer as claimed in claim 3 , further comprising:
a seventh MOS transistor that is a diode-connected NMOS coupled between the input terminal of the fast-transient buffer and the gate terminal of the second MOS transistor to raise an input voltage that the fast-transient buffer receives via the input terminal.
7. The fast-transient buffer as claimed in claim 6 , further comprising:
a fourth current source, coupled to a drain terminal of the seventh MOS transistor to provide a fourth current.
8. The fast-transient buffer as claimed in claim 7 , wherein:
the fourth current equals the first current; and
the seventh MOS transistor is the same size as the second MOS transistor.
9. The fast-transient buffer as claimed in claim 1 , wherein:
the first MOS transistor is an NMOS, and the source terminal of the first MOS transistor is coupled to a ground terminal;
the second MOS transistor is a PMOS;
the third MOS transistor is a PMOS, and a source terminal of the third MOS transistor is coupled to a power terminal; and
the fourth MOS transistor is an NMOS.
10. The fast-transient buffer as claimed in claim 9 , wherein the flipped voltage follower further comprises:
a first current source, coupled to a connection terminal between the gate terminal of the first MOS transistor, the drain terminal of the second MOS transistor and the source terminal of the fourth MOS transistor to sink a first current; and
a second current source, coupled to a connection terminal between the drain terminal of the fourth MOS transistor and the gate terminal of the third MOS transistor to provide a second current.
11. The fast-transient buffer as claimed in claim 10 , wherein the bias circuit comprises:
a fifth MOS transistor that is a diode-connected NMOS; and
a sixth MOS transistor that is a diode-connected NMOS;
wherein the fifth MOS transistor and the sixth MOS transistor are connected in series between the gate terminal of the fourth MOS transistor and the ground terminal.
12. The fast-transient buffer as claimed in claim 11 , wherein the bias circuit further comprises:
a third current source, coupled to a connection terminal between a drain terminal of the sixth transistor and the gate terminal of the fourth transistor to provide a third current.
13. The fast-transient buffer as claimed in claim 10 , further comprising:
a seventh MOS transistor that is a diode-connected PMOS coupled between the input terminal of the fast-transient buffer and the gate terminal of the second MOS transistor to decrease an input voltage that the fast-transient buffer receives via the input terminal.
14. The fast-transient buffer as claimed in claim 13 , further comprising:
a fourth current source, coupled to a drain terminal of the seventh MOS transistor to sink a fourth current.
15. The fast-transient buffer as claimed in claim 14 , wherein:
the fourth current equals the first current; and
the seventh MOS transistor is the same size as the second MOS transistor.