Memory device with defect-free slits
A memory device includes adjacent first and second memory blocks, divided by a slit, in which a cell region and a connection region are divided in a direction perpendicular to the adjacent direction. The slit has a first width between the cell region of the first memory block and the cell region of the second memory block, has the first width between the connection region of the first memory block and the connection region of the second memory block, and has a second width wider than the first width in a region where the cell region and the connection region of the first memory block are adjacent to each other and the cell region and the connection region of the second memory block are adjacent to each other.
1 . A memory device comprising:
a first memory block in which a cell region and a connection region are disposed in a first direction;
a second memory block in which the cell region and the connection region are disposed in the first direction, the second memory block being adjacent to the first memory block in a second direction perpendicular to the first direction; and
a slit between the first and second memory blocks separating the second memory block from the first memory block,
wherein the slit has a first width between the cell region of the first memory block and the cell region of the second memory block, and the slit has the first width between the connection region of the first memory block and the connection region of the second memory block, and the slit has a second width wider than the first width in a region where the cell region and the connection region of the first memory block are adjacent to each other and the cell region and the connection region of the second memory block are adjacent to each other,
wherein the slit includes:
a first expansion hole concave into the first memory block in a region between the cell region and the connection region; and
a second expansion hole concave into the second memory block in a region between the cell region and the connection region.
2 . The memory device of claim 1 ,
wherein the slit has a linear shape except for a region where the first or second expansion hole is formed.
3 . The memory device of claim 1 ,
wherein the first and second memory blocks include first stack structures and second stack structures stacked on the first stack structures.
4 . The memory device of claim 3 ,
wherein a portion of the slit formed between the first stack structures has the second width, and a portion of the slit formed between the second stack structures has the first width.
5 . A memory device comprising:
a first memory block in which a cell region and a connection region are disposed in a first direction;
a second memory block in which the cell region and the connection region are disposed in the first direction, the second memory block being adjacent to the first memory block in a second direction perpendicular to the first direction; and
a slit between the first and second memory blocks separating the second memory block from the first memory block,
wherein the slit has a first width between the cell region of the first memory block and the cell region of the second memory block, and the slit has the first width between the connection region of the first memory block and the connection region of the second memory block, and the slit has a second width wider than the first width in a region where the cell region and the connection region of the first memory block are adjacent to each other and the cell region and the connection region of the second memory block are adjacent to each other,
wherein the slit includes:
a first expansion hole concave into the second memory block; and
a second expansion hole concave into the first memory block.
6 . The memory device of claim 5 ,
wherein the first expansion hole is located in the cell region adjacent to a boundary surface between the cell region and the connection region.
7 . The memory device of claim 5 ,
wherein the second expansion hole is located in the connection region adjacent to a boundary surface between the cell region and the connection region.
8 . The memory device of claim 5 ,
wherein the first and second memory blocks include first stack structures and second stack structures stacked on the first stack structures.
9 . The memory device of claim 8 ,
wherein a portion of the slit formed between the first stack structures has the second width, and a portion of the slit formed between the second stack structures has the first width.