Semiconductor memory device including 3-dimensional structure and method for manufacturing the same
A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.
1. A semiconductor memory device comprising:
a substrate comprising cell regions and a contact region between the cell regions;
a dielectric structure formed over the contact region;
a memory block having cell parts, which are respectively formed over the cell regions, a coupling part, which is formed over the contact region and couples the cell parts, and a through part, which accommodates the dielectric structure;
a peripheral circuit formed over the substrate under the memory block;
bottom wiring lines disposed between the memory block and the peripheral circuit, the bottom wiring lines being electrically coupled with the peripheral circuit;
top wiring lines disposed over the memory block; and
contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.
2. The semiconductor memory device according to claim 1 , wherein the dielectric structure has an elongated shape as viewed from the top extending in a lengthwise direction of the memory block.
3. The semiconductor memory device according to claim 1 , further comprising:
a slit formed between the dielectric structure and the memory block; and
a dielectric sidewall layer filled in the slit.
4. The semiconductor memory device according to claim 3 , wherein the dielectric sidewall layer comprises an oxide-based material.
5. The semiconductor memory device according to claim 1 , further comprising:
at least one support passing through the coupling part.
6. The semiconductor memory device according to claim 5 , wherein the support comprises an oxide-based material.
7. The semiconductor memory device according to claim 1 , wherein the cell parts and the coupling part comprises:
conductive lines and interlayer dielectric layers stacked alternately; and
channel layers passing through the conductive lines and the interlayer dielectric layers of the cell regions.
8. The semiconductor memory device according to claim 7 , wherein the peripheral circuit comprises pass transistors for providing operating voltages to the conductive lines.
9. The semiconductor memory device according to claim 1 , wherein the top wiring lines are formed of a conductive material which has a lower resistance than material forming the bottom wiring lines.