IP Library › Granted Patent US 12,033,711
Granted Patent B2
US 12,033,711 · App. 18/301,327 · Granted Jul 9, 2024

Built-in memory repair with repair code compression

Inventors: Devanathan Varadarajan (Allen, TX); Varun Singh (Plano, TX)
Assignee: Texas Instruments Incorporated
G11C29/4401G11C29/16G11C29/40
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Quick Facts
Patent No.
US 12,033,711
App. No.
18/301,327
Granted
Jul 9, 2024
Kind
B2
Abstract

In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.

Claims (68)

1. An integrated circuit device comprising:

a first memory configured to provide a first set of defect data in a first format that specifies whether a portion of the first memory contains a defect;

a second memory configured to provide a second set of defect data in a second format that specifies whether a portion of the second memory contains a defect, wherein the second format is different from the first format; and

a controller coupled to the first memory and to the second memory and configured to:

convert each of the first set of defect data and the second set of defect data to a third format;

determine a first set of repair data for the first memory based on the first set of defect data in the third format; and

determine a second set of repair data for the second memory based on the second set of defect data in the third format.

2. The integrated circuit device of claim 1 , wherein:

the second memory includes a set of repair cells; and

the third format is based on a count of the set of repair cells of the second memory.

3. The integrated circuit device of claim 1 , wherein:

the second memory has a repair signature format; and

the third format is based on a length of the repair signature format of the second memory.

4. The integrated circuit device of claim 1 , wherein the controller is configured to pad a value in the first set of defect data to produce the first set of defect data in the third format.

5. The integrated circuit device of claim 1 , wherein:

the first memory includes a repair cell; and

the first set of repair data specifies a remapping of an address of a defective element to the repair cell.

6. The integrated circuit device of claim 1 , wherein the controller includes compression circuitry configured to compress the first set of repair data.

7. The integrated circuit device of claim 6 , wherein:

the compression circuitry is a first set of compression circuitry;

the first set of compression circuitry is configured to apply a first compression technique to the first set of repair data; and

the controller includes a second set of compression circuitry configured to compress the second set of repair data by applying a second compression technique that is different from the first compression technique.

8. The integrated circuit device of claim 7 , wherein:

the first compression technique is a look-up table compression technique; and

the second compression technique is a run-length encoding compression technique.

9. The integrated circuit device of claim 6 further comprising a third memory, wherein the controller is configured to store the compressed first set of repair data in the third memory.

10. The integrated circuit device of claim 1 , wherein the controller is configured to determine the second set of repair data by:

splitting the second set of defect data into a first portion associated with a first repair cell and a second portion associated with a second repair cell;

determining a first portion of the second set of repair data based on the first portion of the second set of defect data; and

determining a second portion of the second set of repair data based on the second portion of the second set of defect data.

11. The integrated circuit device of claim 1 , wherein the first set of defect data includes an identifier of the first memory.

12. An integrated circuit device comprising:

a controller that includes:

alignment circuitry configured to:

receive a first set of defect data that specifies whether a portion of a first memory contains a defect, wherein the first set of defect data has a first width;

receive a second set of defect data that specifies whether a portion of a second memory contains a defect, wherein the second set of defect data has a second width that is different from the first width; and

convert each of the first set of defect data and the second set of defect data to have a third width; and

repair circuitry coupled to the alignment circuitry and configured to:

determine a first set of repair data for the first memory based on the first set of defect data; and

determine a second set of repair data for the second memory based on the second set of defect data.

13. The integrated circuit device of claim 12 , wherein the controller further includes compression circuitry coupled to the repair circuitry and configured to:

compress the first set of repair data to produce a first compressed set of repair data; and

compress the second set of repair data to produce a second compressed set of repair data.

14. The integrated circuit device of claim 13 , wherein the controller further includes:

a first register associated with the first memory and configured to store the first compressed set of repair data; and

a second register associated with the second memory and configured to store the second compressed set of repair data.

15. The integrated circuit device of claim 14 , wherein:

the compression circuitry is a first set of compression circuitry; and

the controller further includes a second set of compression circuitry coupled to the first register and to the second register.

16. A method comprising:

receiving a first set of defect data in a first format that specifies whether a portion of a first memory contains a defect;

receiving a second set of defect data in a second format that specifies whether a portion of a second memory contains a defect, wherein the second format is different from the first format;

converting each of the first set of defect data and the second set of defect data to a third format;

determining a first set of repair data for the first memory based on the first set of defect data in the third format; and

determining a second set of repair data for the second memory based on the second set of defect data in the third format.

17. The method of claim 16 , wherein:

the second memory includes a set of repair cells; and

the third format is based on a count of the set of repair cells of the second memory.

18. The method of claim 16 , wherein:

the second memory has a repair signature format; and

the third format is based on a length of the repair signature format of the second memory.

19. The method of claim 16 , wherein:

the first memory includes a repair cell; and

the first set of repair data specifies a remapping of an address of a defective element to the repair cell.

20. The method of claim 16 further comprising:

compressing the first set of repair data to produce a first compressed set of repair data;

compressing the second set of repair data to produce a second compressed set of repair data; and

storing the first compressed set of repair data and the second compressed set of repair data in a memory.

Continuity (2)
Continuation 17125323 · Dec 17, 2020
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