Electronic apparatus and control method thereof
An electronic apparatus may include a processor configured to store data of a user process related to a user area assigned to a first memory or a system process related to a system area assigned to the first memory in a second memory, in response to a memory recovery event for the first memory, and allow an area of the first memory corresponding to at least one of the user area or the system area to store other data, and perform one of restoration of the data based on the access of the first process and restoration of the data based on an access of the second process and prevent the other one from being performed, in response to identification of the access of the second process during the access of the first process to the data stored in the second memory through the system area.
1. An electronic apparatus comprising:
a first memory;
a second memory; and
at least one processor comprising processing circuitry, the at least one processor, individually and/or collectively, configured to:
perform a memory recovery for the first memory, at least by storing data of a user process related to a user area assigned to the first memory and/or a system process related to a system area assigned to the first memory in the second memory, wherein an area of the first memory corresponding to at least one of the user area or the system area is allowed to store other data,
in response to occurring an access of a first process to the data stored in the second memory through the system area, start a restoration of the data stored in the second memory to the first memory according to the access of the first process, and
in response to identifying that there is an access of a second process to the data stored in the second memory before the restoration of the data according to the access of the first process is completed:
(a) complete the restoration of the data according to the access of the first process, and prevent performing a restoration of the data stored in the second memory to the first memory according to the access of the second process, or
(b) start the restoration of the data according to the access of the second process and prevent performing the restoration of the data according to the access of the first process.
2. The electronic apparatus of claim 1 , wherein the at least one processor, individually and/or collectively, is configured to compare the first process and the second process with respect to priority, and execute one of the first process and the second process having a high priority.
3. The electronic apparatus of claim 1 , wherein
the system area comprises a virtual address provided to be assigned to a physical address of the first memory, and
the at least one processor, individually and/or collectively, is configured to prevent the data from being restored based on the virtual address being set to be connected to a physical address of the data, and restore the data based on the virtual address not being set to be connected to a physical address of the data.
4. The electronic apparatus of claim 1 , wherein the at least one processor, individually and/or collectively, is configured to decompress compressed and stored data in the second memory and restore the decompressed data to the first memory.
5. The electronic apparatus of claim 1 , wherein the at least one processor, individually and/or collectively, is configured to put an operation based on the access of the second process on standby, in response to the identification of the access of the second process before completing an operation of storing data of the first process in the second memory during the memory recovery event.
6. The electronic apparatus of claim 1 , wherein
the system area comprises a plurality of virtual addresses provided to be assigned to physical addresses of the first memory, and
the at least one processor, individually and/or collectively, is configured to select data corresponding to a virtual address having a low access count among the plurality of virtual addresses and store the selected data in the second memory during the memory recovery event.
7. The electronic apparatus of claim 6 , wherein the at least one processor, individually and/or collectively, is configured to increase the access count for the virtual address based on a time between a point of storing data corresponding to the virtual address in the second memory and a point of restoring the data to the first memory, the time being shorter than or equal to a threshold, and to decrease the access count based on the time being longer than the threshold.
8. The electronic apparatus of claim 6 , wherein the at least one processor, individually and/or collectively, is configured to increase the access count for the virtual address based on occurrence of multiple accesses to the virtual address.
9. The electronic apparatus of claim 1 , wherein
the system area comprises a virtual address provided to be assigned to a physical address of the first memory, and
the at least one processor, individually and/or collectively, is configured to prevent data of the physical address from being stored in the second memory, based on identification of a direct hardware access of the electronic apparatus to the physical address without using the virtual address during the memory recovery event.
10. The electronic apparatus of claim 1 , wherein the at least one processor, individually and/or collectively, is configured to compress data of the first memory and to store the compressed data in the second memory.
11. The electronic apparatus of claim 1 , wherein the at least one processor, individually and/or collectively, is configured to identify occurrence of the memory recovery event based on an available capacity of the first memory decreasing below a threshold.
12. The electronic apparatus of claim 1 , wherein
the system area comprises a virtual address provided to be assigned to a physical address of the first memory, and
the at least one processor, individually and/or collectively, is configured to identify occurrence of the memory recovery event based on an access to the virtual address disconnected from the physical address.
13. The electronic apparatus of claim 1 , wherein the second process is a kernel process.
14. The electronic apparatus of claim 1 , wherein the first process and the second process are performed during a kernel mode.
15. A method of controlling an electronic apparatus, the method comprising: performing a memory recovery for a first memory, by at least storing data of a user process related to a user area assigned to the first memory and/or a system process related to a system area assigned to the first memory in a second memory, wherein an area of the first memory corresponding to at least one of the user area or the system area is allowed to store other data;
identifying occurring an access of a first process to the data stored in the second memory through the system area;
in response to occurring the access of the first process to the data stored in the second memory through the system area, starting a restoration of the data stored in the second memory to the first memory according to the access of the first process;
identifying that there is an access of a second process to the data stored in the second memory before the restoration of the data according to the access of the first process is completed; and
in response to identifying that there is the access of the second process to the data stored in the second memory before the restoration of the data according to the access of the first process is completed;
(a) completing the restoration of the data according to the access of the first process, and preventing performing a restoration of the data stored in the second memory to the first memory according to the access of the second process, or
(b) starting the restoration of the data according to the access of the second process and preventing performing the restoration of the data according to the access of the first process.
16. The method of claim 15 , further comprising comparing the first process and the second process with respect to priority, and executing one of the first process and the second process having a high priority.
17. The method of claim 15 , wherein
the system area comprises a virtual address provided to be assigned to a physical address of the first memory, and
the method further comprising preventing the data from being restored based on the virtual address being set to be connected to a physical address of the data, and restoring the data based on the virtual address not being set to be connected to a physical address of the data.
18. The method of claim 15 , wherein the system area comprises a plurality of virtual addresses provided to be assigned to physical addresses of the first memory, and the method comprises: selecting data corresponding to a virtual address having a low access count among the plurality of virtual addresses and store the selected data in the second memory during the memory recovery event.
19. The method of claim 18 , comprising increasing an access count for the virtual address having the low access count based on a time between a point of storing data corresponding to the virtual address having the low access count in the second memory and a point of restoring the data to the first memory, the time being shorter than or equal to a threshold, and to decrease the access count based on the time being longer than the threshold.