Clock mode determination in a memory system
A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
1. A configurable memory device having a first operating mode and a second operating mode, the configurable memory device comprising:
a plurality of memory blocks to store user data;
a chip enable port configured to receive a chip enable signal for enabling the configurable memory device;
a first clock input port configured to receive a first clock input signal;
a second clock input port configured to receive a second clock input signal, the second clock input signal being complementary to the first clock input signal;
a clock output port configured to transmit a clock output signal when the configurable memory device is configured to the first operating mode, wherein the clock output signal is referenced to the first clock input signal;
one or more common data ports configured to transfer common data signals carrying command data, address data, input data and output data, the input data to be written into one of the plurality of memory blocks accessible based on the command data and the address data, and the output data to be retrievable from the one of the plurality of memory blocks;
a clock input circuitry configurable, to a differential signaling configuration when the configurable memory device is configured to the first operating mode, and to a single ended signaling configuration when the configurable memory device is configured to the second operating mode, the differential signaling configuration for utilizing the first clock input signal and the second clock input signal as differential signals, and the single ended signaling configuration for utilizing one of the first clock input signal and the second clock input signal as a single ended signal; and
one or more output buffers configurable to one of a plurality of output buffer drive strengths to transfer the output data retrieved from the one of the plurality of memory blocks, wherein the output data is synchronized with the clock output signal when the configurable memory device is configured to the first operating mode.
2. The configurable memory device of claim 1 , wherein the configurable memory device is automatically configured to one of the first operating mode and the second operating mode during a power on reset sequence.
3. The configurable memory device of claim 1 , wherein the output data is edge aligned with the clock output signal.
4. The configurable memory device of claim 1 , wherein the configurable memory device is configured to one of the first operating mode and the second operating mode in response to an external voltage level.
5. The configurable memory device of claim 1 , further comprising:
a reference voltage port; and
a clock mode configuration circuit configured to enable one of the first operating mode and the second operating mode in response to a voltage at the reference voltage port.
6. The configurable memory device of claim 1 , further comprising a reset port configured to receive a reset signal for resetting the configurable memory device to a power up default configuration.
7. The configurable memory device of claim 1 , wherein the power up default configuration is the single ended signaling configuration.
8. The configurable memory device of claim 1 , wherein the configurable memory device is a non-volatile memory device.
9. The configurable memory device of claim 1 , wherein the configurable memory device is a random access memory device.
10. The configurable memory device of claim 1 , wherein the command data, address data and input data are latched on the rising and falling edges of the first clock input signal when the configurable memory device is configured to the first operating mode.
11. A configurable memory device comprising:
a plurality of memory blocks to store user data;
a chip enable port configured to receive a chip enable signal for enabling the configurable memory device;
a first clock input port configured to receive a first clock input signal;
a second clock input port configured to receive a second clock input signal, the second clock input signal being complementary to the first clock input signal;
a clock output port configured to transmit a clock output signal, wherein the clock output signal is referenced to the first clock input signal;
one or more common data ports configured to transfer common data signals carrying command data, address data, input data and output data, the input data to be written into one of the plurality of memory blocks accessible based on the command data and the address data, and the output data to be retrievable from the one of the plurality of memory blocks, wherein the command data, address data and input data are latched on the rising and falling edges of the first clock input signal;
a configurable clock input buffer configurable to one of a single ended signaling configuration and a differential signaling configuration, the differential signaling configuration for utilizing the first clock input signal and the second clock input signal as differential signals, and the single ended signaling configuration for utilizing one of the first clock input signal and the second clock input signal as a single ended signal; and
one or more configurable output buffers configurable to one of a plurality of output buffer drive strengths to transfer the output data retrieved from the one of the plurality of memory blocks, wherein the output data is edge aligned with the rising and falling edges of the clock output signal.
12. The configurable memory device of claim 11 , wherein the configurable memory device is automatically configured to the single ended signaling configuration during a power on reset sequence.
13. The configurable memory device of claim 11 , further comprising a reset port configured to receive a reset signal for resetting the configurable memory device to a power up default configuration.
14. The configurable memory device of claim 13 , wherein the power up default configuration is the single ended signaling configuration.
15. The configurable memory device of claim 11 , wherein the configurable memory device is configured to one of the single ended signaling configuration and the differential signaling configuration in response to an external voltage level.
16. The configurable memory device of claim 11 , further comprising:
a reference voltage port; and
a clock mode configuration circuit configured to select one of the single ended signaling configuration and the differential signaling configuration in response to a voltage at the reference voltage port.
17. The configurable memory device of claim 11 , wherein the configurable memory device is a non-volatile memory device.
18. The configurable memory device of claim 11 , wherein the configurable memory device is a NOR flash memory device.
19. The configurable memory device of claim 11 , wherein the configurable memory device is a NAND flash memory device.
20. The configurable memory device of claim 11 , wherein the configurable memory device is a random access memory device.