IP Library Granted Patent US 12,107,003
Granted Patent B2
US 12,107,003 · App. 18/303,839 · Granted Oct 1, 2024

Etch profile control of gate contact opening

Inventors: Te-Chih Hsiung (Taipei, TW); Yi-Chun Chang (Hsinchu, TW); Jyun-De Wu (New Taipei, TW); Yi-Chen Wang (Hsinchu County, TW); Yuan-Tien Tu (Chiayi County, TW); Huan-Just Lin (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/76826H01L21/76802H01L21/76804H01L21/76831H01L21/76832H01L23/5226H01L23/53295H01L21/31116H01L21/76877
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Quick Facts
Patent No.
US 12,107,003
App. No.
18/303,839
Granted
Oct 1, 2024
Kind
B2
Abstract

A semiconductor device includes a gate structure, source/drain regions, source/drain contacts, a gate dielectric cap, an etch stop layer, and a gate contact. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The source/drain contacts are over the source/drain regions, respectively. The gate dielectric cap is over the gate structure and has opposite sidewalls interfacing the source/drain contacts.

Claims (36)

1. A device, comprising: a gate structure over a substrate; source/drain regions at opposite sides of the gate structure; source/drain contacts over the source/drain regions, respectively; a gate dielectric cap over the gate structure and having opposite sidewalls interfacing the source/drain contacts; a nitride-based etch stop layer over the source/drain contacts and the gate dielectric cap; and a gate contact extending through the nitride-based etch stop layer and the gate dielectric cap to electrically connect with the gate structure, wherein the nitride-based etch stop layer has an oxidized region interfacing opposite sidewalls of the gate contact.

2. The device of claim 1 , wherein an interface formed by the oxidized region of the nitride-based etch stop layer and the gate contact is slant.

3. The device of claim 1 , wherein an interface formed by the oxidized region of the nitride-based etch stop layer and the gate contact is vertical.

4. The device of claim 1 , further comprising:

a metal cap between the gate dielectric cap and the gate structure.

5. The device of claim 4 , wherein the metal cap is fluorine-free tungsten.

6. The device of claim 1 , further comprising:

gate spacers spacing apart the source/drain contacts from the gate structure.

7. The device of claim 6 , wherein the gate dielectric cap is further over the gate spacers.

8. The device of claim 1 , wherein the device is a fin field-effect transistor (FinFET) or a gate-all-around (GAA) transistor.

9. A device, comprising:

a source region and a drain region over a substrate;

a channel region between the source region and the drain region;

a gate structure over the channel region;

a dielectric cap over the gate structure;

a nitride-based etch stop layer over the dielectric cap, the nitride-based etch stop layer having an oxidized region over the gate structure; and

a gate contact extending through the oxidized region of the nitride-based etch stop layer and the dielectric cap to the gate structure.

10. The device of claim 9 , wherein the nitride-based etch stop layer has an un-oxidized region over the source region.

11. The device of claim 9 , wherein the nitride-based etch stop layer has an un-oxidized region over the drain region.

12. The device of claim 9 , wherein the dielectric cap has an oxidized region below the oxidized region of the nitride-based etch stop layer.

13. The device of claim 12 , wherein the oxidized region of the dielectric cap continuously extends from the oxidized region of the nitride-based etch stop layer.

14. The device of claim 9 , further comprising:

an interlayer dielectric over the nitride-based etch stop layer, wherein an interface between the gate contact and the oxidized region of the nitride-based etch stop layer is aligned with an interface between the gate contact and the interlayer dielectric.

15. A device, comprising:

a gate structure over a substrate;

a source region and a drain region at opposite sides of the gate structure;

a source contact over the source region;

a drain contact over the drain region; and

a nitride-based etch stop layer over the gate structure, the source contact, and the drain contact, the nitride-based etch stop layer having an oxidized region over the gate structure, and an un-oxidized region over the source contact and the drain contact.

16. The device of claim 15 , wherein the oxidized region of the nitride-based etch stop layer has a smaller width than the un-oxidized region of the nitride-based etch stop layer.

17. The device of claim 15 , further comprising:

a gate contact laterally surrounded by the oxidized region of the nitride-based etch stop layer.

18. The device of claim 15 , further comprising:

a dielectric cap laterally between the source contact and the drain contact, the dielectric cap spacing apart the nitride-based etch stop layer from the gate structure.

19. The device of claim 18 , wherein the dielectric cap comprises an oxidized region over the gate structure and an un-oxidized region interfacing the source contact and the drain contact.

20. The device of claim 19 , wherein the oxidized region of the dielectric cap is directly below the oxidized region of the oxidized region of the nitride-based etch stop layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: HSIUNG, TE-CHIH; CHANG, YI-CHUN; WU, JYUN-DE; WANG, YI-CHEN; TU, YUAN-TIEN; LIN, HUAN-JUST
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 063420/0132 →
Continuity (3)
Continuation 17181768 · Feb 22, 2021
Provisional Application 63084722 · Sep 29, 2020
Related Publication 20230298934A1 · Sep 21, 2023