Memory device related to a verify operation and method of operating the memory device
A memory device includes a plurality of memory cells programmed to a first program state through a plurality of program loops, a page buffer configured to perform a verify operation of verifying the first program state in each of the plurality of program loops, and control logic configured to, as the plurality of program loops are sequentially performed, adjust a first evaluation time of a first evaluation operation so as to decrease the difference between a second evaluation time of a second evaluation operation and the first evaluation time.
1. A memory device comprising:
a plurality of memory cells programmed to a first program state through a plurality of program loops;
a page buffer configured to apply a program voltage to the plurality of memory cells, to perform a first verify operation of verifying the first program state based on a first evaluation time, and to perform a second verify operation of verifying the first program state based on a second evaluation time, in each of the plurality of program loops; and
control logic configured to, as the plurality of program loops are sequentially performed, adjust the first evaluation time so as to decrease the difference between the second evaluation time and the first evaluation time.
2. The memory device of claim 1 , wherein the first evaluation time is shorter than the second evaluation time.
3. The memory device of claim 2 , wherein the control logic increases the first evaluation time as the plurality of program loops are sequentially performed.
4. The memory device of claim 3 , wherein the control logic maintains the second evaluation time in the plurality of program loops.
5. The memory device of claim 1 , wherein the first program state is any one of a plurality of program states classified based on a threshold voltage.
6. The memory device of claim 1 , wherein the page buffer performs the first evaluation operation based on a first evaluation time and performs a second evaluation operation based on the second evaluation time, when a verify voltage is applied to a word line connected to the plurality of memory cells.
7. A method of operating a memory device, the method comprising:
applying a first program voltage to a plurality of memory cells in a first program loop;
performing a first verify operation of verifying a first program state of the plurality of memory cells based on a first evaluation time in the first program loop;
performing a second verify operation of verifying the first program state based on a second evaluation time in the first program loop;
increasing the first evaluation time;
applying a second program voltage to the plurality of memory cells in a second program loop;
performing the first verify operation of verifying the first program state based on the increased first evaluation time in the second program loop; and
performing the second verify operation of verifying the first program state based on the second evaluation time in the second program loop.
8. The method of claim 7 , wherein performing the first verify operation in the first program loop comprises:
precharging bit lines connected to the plurality of memory cells;
performing a first evaluation operation of evaluating a threshold voltage of the plurality of memory cells according to the first evaluation time; and
storing data sensed according to a voltage of the bit lines in a latch.
9. The method of claim 8 , wherein performing the first verify operation in the second program loop comprises:
precharging the bit lines;
performing the first evaluation operation according to the increased first evaluation time; and
storing the data sensed according to the voltage of the bit lines in the latch.
10. The method of claim 7 , wherein performing the second verify operation in the first program loop or the second program loop comprises:
precharging bit lines connected to the plurality of memory cells;
performing a second evaluation operation of evaluating a threshold voltage of the plurality of memory cells according to the second evaluation time; and
storing data sensed according to a voltage of the bit lines in a latch.
11. The method of claim 7 , wherein the increased first evaluation time is shorter than the second evaluation time.
12. A memory device comprising:
a plurality of memory cells programmed to any one program state among a plurality of program states;
a page buffer configured to perform a first verify operation and a second verify operation of verifying the program state in a program loop;
an evaluation time controller configured to increase a first evaluation time of a first evaluation operation included in the first verify operation and maintain a second evaluation time of a second evaluation operation included in the second verify operation whenever the program loop is changed; and
a page buffer controller configured to control the page buffer to perform the first evaluation operation based on the first evaluation time and perform the second evaluation operation based on the second evaluation time.
13. The memory device of claim 12 , wherein the evaluation time controller increases the first evaluation time by a unit time.
14. The memory device of claim 12 , wherein the evaluation time controller sets the first evaluation time to an initial value in a program loop in which the first verify operation and the second verify operation are first started.