Systems and methods for predictive memory maintenance
Embodiments of the present disclosure include techniques for predictive memory maintenance. In one embodiment, locations of correctable errors in a memory are observed. A machine learning (ML) system may be trained with patterns of correctable errors that result in uncorrectable errors. A trained ML monitors correctable errors to predict when memory requires maintenance. In another embodiment, error rates from multiple memories are monitored to predict memory channel and other upstream device failures.
1. A method of managing memory errors comprising:
receiving memory error locations;
processing a plurality of values corresponding to the memory error locations in a machine learning system configured to recognize patterns of correctable error locations resulting in uncorrectable errors; and
generating an alert when the machine learning system recognizes a pattern of the error locations corresponding to an uncorrectable error.
2. The method of claim 1 , wherein the memory error locations correspond to correctable memory errors.
3. The method of claim 1 , wherein the plurality of values is received in the machine learning system as a two-dimensional array of values, and wherein positions in the two-dimensional array correspond to the memory error locations.
4. The method of claim 3 , wherein the memory error locations are processed in predefined frames, and wherein the predefined frames are a subset of the two-dimensional array of values.
5. The method of claim 1 , wherein the memory error locations are received over a time period, and wherein the plurality of values aggregates the received memory error locations over the time period.
6. The method of claim 1 , wherein the plurality of values is a plurality of binary values.
7. The method of claim 1 , wherein the plurality of values is a plurality of values between a maximum value and a minimum value.
8. The method of claim 7 , wherein a first value of the plurality of values corresponds to a number of times a particular error occurs at a particular memory error location.
9. The method of claim 7 , wherein a first value of the plurality of values corresponds to an error rate.
10. The method of claim 7 , wherein a first value of the plurality of values corresponds to a number of bits read between errors for a particular memory error location.
11. The method of claim 1 , wherein the plurality of values corresponding to the memory error locations are a first plurality of values, the method further comprising processing a second plurality of values corresponding to the memory error locations in a machine learning system configured to recognize patterns of correctable error locations resulting in uncorrectable errors, wherein the first plurality of values corresponds to aggregated memory error locations over a first time period and the second plurality of values corresponds to aggregated memory error locations over a second time period.
12. The method of claim 1 , wherein the plurality of memory error locations are a first plurality of memory error locations and the plurality of values corresponding to the memory error locations are a first plurality of values, the method further comprising;
storing a second plurality of memory error locations;
converting the second plurality of memory error locations into a second plurality of values;
detecting uncorrectable errors for at least a portion of the second plurality of memory error locations; and
training the machine learning system using the second plurality of values and the detected uncorrectable errors to recognize patterns of correctable error locations resulting in uncorrectable errors.
13. The method of claim 12 , further comprising associating values corresponding to an aggregated plurality of memory error locations with an uncorrectable error value when an uncorrectable error occurs subsequent to a plurality of correctable errors in the aggregated plurality of memory error locations.
14. The method of claim 1 , wherein the machine learning system is a convolutional neural network.
15. The method of claim 1 , wherein the memory is a dynamic random access memory on a dual in-line memory module comprising a plurality of dynamic random access memories.
16. The method of claim 1 , wherein the memory error locations comprise first memory error data from a plurality of random access memories coupled to a memory controller over a memory channel, the method further comprising:
determining a memory error rate from the first memory error data;
comparing the memory error rate to a threshold; and
eliminating the first memory error data from the memory error locations when the memory error rate is above the threshold.
17. A system for managing memory errors comprising:
at least one processor;
at least one non-transitory computer readable medium storing computer executable instructions that, when executed by the at least one processor, cause the system to perform actions comprising:
receiving memory error locations;
processing a plurality of values corresponding to the memory error locations in a machine learning system configured to recognize patterns of correctable error locations resulting in uncorrectable errors; and
generating an alert when the machine learning system recognizes a pattern of the error locations corresponding to an uncorrectable error.
18. The system of claim 17 , wherein the memory is a dynamic random access memory on a dual in-line memory module comprising a plurality of dynamic random access memories.
19. A non-transitory computer-readable medium storing computer-executable instructions that, when executed by at least one processor, perform a method of managing memory errors, the method comprising:
receiving memory error locations;
processing a plurality of values corresponding to the memory error locations in a machine learning system configured to recognize patterns of correctable error locations resulting in uncorrectable errors; and
generating an alert when the machine learning system recognizes a pattern of the error locations corresponding to an uncorrectable error.
20. The non-transitory computer-readable medium of claim 19 , wherein the memory is a dynamic random access memory on a dual in-line memory module comprising a plurality of dynamic random access memories.