Non-volatile semiconductor memory device and method of manufacturing the same

1 . A semiconductor device, comprising:

a first source region and a drain region disposed on a substrate;

a first gate stack comprising a first floating gate and a first control gate, and disposed between the first source region and the drain region;

a first select gate disposed on one sidewall of the first gate stack;

a first spacer disposed on a lower sidewall of the first select gate, and disposed adjacent to the first source region;

a second spacer disposed on an upper sidewall of the first select gate;

a first control gate silicide layer disposed on the first control gate; and

a first select gate silicide layer disposed on the first select gate, and disposed between the first spacer and the second spacer.

2 . The semiconductor device of claim 1 , further comprising:

a third spacer disposed on the other sidewall of the first gate stack and disposed adjacent to the drain region.

3 . The semiconductor device of claim 1 , further comprising:

a first tunneling gate insulation layer disposed between the first floating gate and the substrate;

a first select gate insulation layer disposed between the first select gate and the substrate;

a drain silicide layer disposed on the drain region; and

a first source silicide layer disposed on the first source region.

4 . The semiconductor device of claim 1 , wherein the first select gate has a height lower than a height of the first control gate silicide layer.

5 . The semiconductor device of claim 1 , wherein the second spacer contacts the first select gate, the first control gate silicide layer, and the first select gate silicide layer.

6 . The semiconductor device of claim 2 , further comprising:

a second source region disposed on the substrate;

a second gate stack comprising a second floating gate and a second control gate, and disposed between the second source region and the drain region;

a second select gate disposed on one sidewall of the second gate stack; and

a second select gate insulation layer disposed between the second select gate and the substrate.

7 . The semiconductor device of claim 6 , further comprising:

a fourth spacer disposed on a lower sidewall of the second select gate, and disposed adjacent to the second source region;

a fifth spacer disposed on an upper sidewall of the second select gate;

a second control gate silicide layer disposed on the second control gate; and

a second select gate silicide layer disposed on the second select gate, and disposed between the fourth spacer and the fifth spacer.

8 . The semiconductor device of claim 7 , further comprising:

a sixth spacer disposed on the other sidewall of the second gate stack, and disposed adjacent to the drain region.

9 . A semiconductor device, comprising:

a gate stack comprising a floating gate and a control gate disposed on a substrate;

a select gate disposed on one sidewall of the gate stack;

a select gate insulation layer disposed between the substrate and the select gate;

a control gate silicide layer disposed on the control gate;

a select gate silicide layer disposed on the select gate;

a first spacer disposed on a lower sidewall of the select gate;

a second spacer disposed on an upper sidewall of the select gate; and

a third spacer disposed on the other sidewall of the gate stack,

wherein the select gate silicide layer is disposed between the first spacer and the second spacer.

10 . The semiconductor device of claim 9 , further comprising:

a source region disposed adjacent to the first spacer;

a drain region disposed adjacent to the third spacer;

a source silicide layer disposed on the source region;

a drain silicide layer disposed on the drain region; and

an etch-stop layer disposed on the source and drain silicide layers.

11 . The semiconductor device of claim 9 , wherein the select gate has a height lower than a height of the control gate silicide layer.

12 . The semiconductor device of claim 9 , wherein the second spacer contacts the select gate, the control gate silicide layer, and the select gate silicide layer.

13 . The semiconductor device of claim 9 , wherein the gate stack further comprises:

a tunneling gate insulation layer disposed between the floating gate and the substrate; and

a dielectric layer disposed between the floating gate and the control gate.