Computer system with instruction pre-sending
A computer architecture provides a pre-sending of memory blocks from a lower level memory hierarchy component to a higher level memory hierarchy component using a table linking a set of memory blocks holding instructions that are executed in different fragments of a program. The table is used to pre-send memory blocks to the higher level memory hierarchy component in anticipation of their use by a processor executing the program.
1. A computer architecture comprising:
a processor;
a memory hierarchy providing a lower level component and a higher level component providing faster access by the processor than the lower level component, the lower level component holding a portion of a program in defined memory blocks; and
an instruction pre-sending unit communicating with the processor and the lower level component and operating during execution of a program by the processor to:
(1) maintain a table linking a first instruction of the program to a first set of memory blocks and to a second instruction of the program, the second instruction linked to a second set of memory blocks and succeeding the first instruction in an execution of the program;
(2) maintain a stack to identify the second set of memory blocks linked to the second instruction; and
(3) use the table in conjunction with the stack to pre-send a memory block from the first set of memory blocks and from the second set of memory blocks from a lower level component of the memory hierarchy to a higher level component of the memory hierarchy.
2. The computer architecture of claim 1 wherein the each memory block in the first set of memory blocks and the each memory block in the second set of memory blocks is a cache block.
3. The computer architecture of claim 1 wherein the first and second sets of memory blocks are defined by corresponding portions of the program delineated by call instructions or return instructions of the program.
4. The computer architecture of claim 1 wherein the table provides a logical graph of the program having sets of memory blocks as nodes linked by directed edges indicating execution order.
5. The computer architecture of claim 1 wherein the table links a given first instruction and first set of memory blocks to two or more second instructions and second sets of memory blocks.
6. The computer architecture of claim 5 wherein the table assigns path aging bits to each of the two or more second instructions and the pre-sending unit operates to pre-send a memory block from a given second set of memory blocks based upon the value of the path aging bits of the second instruction associated with the given second set of memory blocks.
7. The computer architecture of claim 1 wherein at (3), the instruction pre-sending unit determines whether a memory block from a given set of memory blocks is currently in the higher level component and pre-sends the memory block to the higher level component based on that determination.
8. The computer architecture of claim 1 wherein the instruction pre-sending unit further operates during execution of the program by the processor to:
(4) repeat (3) with the first instruction associated with the first set of memory blocks in a given repetition being the second instruction associated with the second set of memory blocks of the previous repetition with the second set of memory blocks in the given repetition being a new third set of memory blocks.
9. The computer architecture of claim 8 wherein the instruction pre-sending unit performs at least two repetitions without communication with the processor.
10. The computer architecture of claim 8 wherein the instruction pre-sending unit periodically receives from the processor an identifier of proximately executing memory blocks to control the number of repetitions.
11. The computer architecture of claim 8 wherein the instruction pre-sending unit maintains the table by monitoring execution of the program.
12. The computer architecture of claim 1 wherein the first instruction of the program and second instruction of the program in the table are identified by a compressed representation of the program counter values of the first instruction of the program and of the second instruction of the program.
13. The computer architecture of claim 1 wherein the table is set associative.
14. The computer architecture of claim 1 wherein the stack is maintained by pushing information identifying the second set of blocks onto the stack when the second instruction is not a return instruction and by popping information identifying the second set of blocks from the stack when the second instruction is a return instruction.
15. A computer architecture comprising:
a processor;
a memory hierarchy providing a lower level component and a higher level component providing faster access by the processor than the lower level component, the lower level component holding a portion of a program in defined memory blocks; and
an instruction pre-sending unit communicating with the processor and the lower level component and operating during execution of a program by the processor to:
(1) maintain a table linking a first instruction of the program to a first set of memory blocks and to a second instruction of the program, the second instruction linked to a second set of memory blocks and succeeding the first instruction in an execution of the program;
(2) use the table to pre-send a memory block from the first set of memory blocks and from the second set of memory blocks from a lower level component of the memory hierarchy to a higher level component of the memory hierarchy;
wherein the table links a given first instruction and first set of memory blocks to two or more second instructions and second sets of memory blocks; and
wherein the instruction pre-sending unit operates to pre-send a memory block from each of the corresponding two or more second sets of memory blocks.
16. A method of managing memory blocks in a computer architecture having a processor and a memory hierarchy providing a lower level component and a higher level component providing faster access by the processor than the lower level component, the lower level component holding a portion of a program in defined memory blocks; the method comprising:
(1) maintaining a table linking a first instruction of the program to a first set of memory blocks and to a second instruction of the program, the second instruction linked to a second set of memory blocks and succeeding the first instruction in an execution of the program;
(2) maintain a stack to identify the second set of memory blocks linked to the second instruction; and
(3) using the table in conjunction with the stack to pre-send a memory block from the first set of memory blocks and from the second set of memory blocks from a lower level component of the memory hierarchy to a higher level component of the memory hierarchy.
17. The method of claim 16 wherein each memory block in the first set of memory blocks and each memory block in the second set of memory blocks is a cache block.
18. The method of claim 16 wherein the first and second sets of memory blocks are defined by corresponding portions of the program delineated by call instructions or return instructions of the program.
19. The method of claim 16 wherein the table provides a logical graph of the program having sets of memory blocks as nodes linked by directed edges indicating historical execution order.
20. The method of claim 16 wherein the table links a given first instruction and first set of memory blocks to two or more second instructions and second sets of memory blocks.
21. The method of claim 20 wherein the table assigns path aging bits to each of the two or more second instructions and the pre-sending unit operates to pre-send a memory block from a given second set of memory blocks based upon the value of the path aging bits of the second instruction associated with the given second set of memory blocks.
22. The method of claim 16 wherein at (3), further including determining whether a memory block from a given set of memory blocks is currently in the higher level component and pre-sending the memory block to the higher level component based on that determination.
23. The method of claim 16 further including repeating (3) with the first instruction associated with the first set of memory blocks in a given repetition being the second instruction associated with the second set of memory blocks of the previous repetition with the second set of memory blocks in the given repetition being a new third set of memory blocks.
24. The method of claim 23 including identifying a proximately executing memory block to control the number of repetitions.
25. The computer architecture of claim 16 where in the table is maintained by monitoring the execution of the program.
26. The method of claim 16 wherein the first instruction of the program and the second instruction of the program in the table are identified by a compressed representation of the program counter values of the first instruction of the program and of the second instruction of the program.
27. A method of managing memory blocks in a computer architecture having a processor and a memory hierarchy providing a lower level component and a higher level component providing faster access by the processor than the lower level component, the lower level component holding a portion of a program in defined memory blocks; the method comprising:
(1) maintaining a table linking a first instruction of the program to a first set of memory blocks and to a second instruction of the program, the second instruction linked to a second set of memory blocks and succeeding the first instruction in an execution of the program;
(2) using the table to pre-send a memory block from the first set of memory blocks and from the second set of memory blocks from a lower level component of the memory hierarchy to a higher level component of the memory hierarchy;
wherein the table links a given first instruction and first set of memory blocks to two or more second instructions and second sets of memory blocks; and
further including pre-sending a memory block from each of the corresponding two or more second sets of memory blocks.