Semiconductor transistor devices including nanostructures between dielectric walls and methods of manufacturing
A device includes a first stack of nanostructures formed over a substrate; a second stack of nanostructures formed adjacent to the first stack; a first gate structure on the nanostructures of the first stack; a second gate structure on the nanostructures of the second stack; a first insulating wall separating the first gate structure and the second gate structure; a hard mask layer on the first gate structure and on the second gate structure; and a gate contact extending through the hard mask layer to physically and electrically contact the first gate structure.
1 . A device comprising:
a first stack of nanostructures formed over a substrate;
a second stack of nanostructures formed adjacent to the first stack;
a first gate structure on the first stack of nanostructures;
a second gate structure on the second stack of nanostructures;
a first insulating wall separating the first gate structure and the second gate structure;
a hard mask layer on the first gate structure and on the second gate structure; and
a gate contact extending through the hard mask layer to physically and electrically contact the first gate structure, wherein a bottom surface of the gate contact is closer to the substrate than a top surface of the first insulating wall.
2 . The device of claim 1 , wherein the first insulating wall is along a first side of the first gate structure, and further comprising a second insulating wall along a second side of the first gate structure.
3 . The device of claim 1 , wherein the gate contact extends over the first insulating wall to physically and electrically contact the second gate structure.
4 . The device of claim 1 , wherein a portion of the first insulating wall extends over the hard mask layer.
5 . The device of claim 1 , wherein the hard mask layer has a thickness in a range of 4 nm to 8 nm.
6 . The device of claim 1 further comprising a source/drain region adjacent the first stack of nanostructures, wherein a top surface of the source/drain region is lower than a top surface of the hard mask layer.
7 . The device of claim 1 , wherein the first insulating wall has a width in a range of 10 nm to 30 nm.
8 . A device comprising:
a first dielectric wall over a substrate;
a second dielectric wall over the substrate, wherein the second dielectric wall is adjacent the first dielectric wall;
a plurality of nanostructures between the first dielectric wall and the second dielectric wall;
a gate stack on each nanostructure of the plurality of nanostructures, wherein the gate stack comprises a gate electrode over a gate dielectric, wherein the gate stack is sandwiched between the first dielectric wall and the second dielectric wall; and
a hard mask on the gate stack, wherein the hard mask is sandwiched between the first dielectric wall and the second dielectric wall.
9 . The device of claim 8 , wherein the gate dielectric physically contacts the first dielectric wall and the gate electrode physically contacts the second dielectric wall.
10 . The device of claim 8 , wherein the first dielectric wall is a different dielectric material than the second dielectric wall.
11 . The device of claim 8 , wherein a top surface of the second dielectric wall and a top surface of the hard mask are level.
12 . The device of claim 8 , wherein a width of the hard mask is greater than a width of the nanostructures of the plurality of nanostructures.
13 . The device of claim 8 , wherein a lateral thickness of the gate electrode between a nanostructure of the plurality of nanostructures and the second dielectric wall is in a range of 3 nm to 10 nm.
14 . The device of claim 8 , wherein a vertical thickness of the gate electrode between a nanostructure of the plurality of nanostructures and the hard mask is in a range of 4 nm to 10 nm.
15 . A method comprising:
forming a first stack of nanostructures over a substrate;
forming a hard mask on the first stack of nanostructures;
after forming the hard mask, forming a gate structure on the first stack of nanostructures;
forming a first isolation wall on a first side of the first stack of nanostructures and a first side of the hard mask;
forming a second isolation wall on a second side of the first stack of nanostructures and a second side of the hard mask; and
forming a contact extending through the hard mask and contacting the gate structure.
16 . The method of claim 15 , wherein forming the first isolation wall comprises:
forming a dummy gate over the hard mask and adjacent the first stack of nanostructures;
etching the dummy gate using the hard mask as an etch mask to form a recess adjacent the first stack of nanostructures; and
depositing a dielectric material in the recess.
17 . The method of claim 15 , wherein forming the hard mask comprises:
forming a sacrificial material on the first stack of nanostructures;
removing the sacrificial material to form an opening; and
depositing a hard mask material in the opening.
18 . The method of claim 17 , wherein the sacrificial material comprises silicon-germanium.
19 . The method of claim 15 , wherein forming the gate structure comprises:
depositing an electrode material over the first stack of nanostructures;
depositing a mask layer on a sidewall of the electrode material;
after depositing the mask layer, performing an etch process to remove excess electrode material; and
removing the mask layer.
20 . The method of claim 19 further comprising, after removing the mask layer, depositing additional electrode material over the first stack of nanostructures.