IP Library › Granted Patent US 11,955,955
Granted Patent B2
US 11,955,955 · App. 18/312,230 · Granted Apr 9, 2024

HEMT-based driver circuit and method of operating the same

Inventor: Ming Hsien Tsai (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H03K17/08122H02M1/08H02M1/32
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Quick Facts
Patent No.
US 11,955,955
App. No.
18/312,230
Granted
Apr 9, 2024
Kind
B2
Abstract

A circuit includes power supply and reference nodes, a protection circuit including a first output terminal and first and second series of n-type HEMTs coupled between the power supply and reference nodes, and a gate driver including a second output terminal and third through fifth series of n-type HEMTs coupled between the power supply and reference nodes. The first HEMT series controls a first node voltage responsive to a power supply node voltage, the second HEMT series controls a first output terminal voltage responsive to the first node voltage, the third HEMT series controls an internal signal on a second node responsive to the first output terminal voltage and to an input signal, the fourth HEMT series controls a third node voltage responsive to the internal signal, and the fifth HEMT series controls a signal at the second output terminal responsive to the internal signal and the third node voltage.

Claims (88)

1. A circuit comprising:

a power supply node;

a power supply reference node;

a protection circuit comprising a first output terminal and first and second series of n-type high electron mobility transistors (HEMTs) coupled between the power supply node and the power supply reference node; and

a gate driver comprising a second output terminal and third through fifth series of n-type HEMTs coupled between the power supply node and the power supply reference node,

wherein

the first series of n-type HEMTs is configured to control a first voltage on a first node responsive to a power supply voltage on the power supply node,

the second series of n-type HEMTs is configured to control a second voltage on the first output terminal responsive to the first voltage,

the third series of n-type HEMTs is configured to control an internal signal on a second node responsive to the second voltage and to an input signal,

the fourth series of n-type HEMTs is configured to control a third voltage on a third node responsive to the internal signal, and

the fifth series of n-type HEMTs is configured to control an output signal at the second output terminal responsive to the internal signal and the third voltage.

2. The circuit of claim 1 , wherein

the protection circuit further comprises a voltage divider configured to generate a fourth voltage based on the power supply voltage,

the first series of n-type HEMTs comprises a depletion-mode n-type HEMT coupled between the power supply node and the first node and a first enhancement-mode n-type HEMT coupled between the first node and the power supply reference node,

the depletion-mode n-type HEMT is configured as a diode, and

the first enhancement-mode n-type HEMT comprises a gate configured to receive the fourth voltage.

3. The circuit of claim 2 , wherein

the voltage divider comprises:

a series of voltage divider components coupled between the power supply node and the power supply reference node; and

a second enhancement-mode n-type HEMT arranged in parallel with a first voltage divider component of the series of voltage divider components,

wherein

the series of voltage divider components comprises a voltage tap coupled to the gate of the first enhancement-mode n-type HEMT, and

the second enhancement-mode n-type HEMT comprises a gate coupled to the first node.

4. The circuit of claim 1 , wherein

the second series of n-type HEMTs comprises a depletion-mode n-type HEMT coupled between the power supply node and the first output terminal and an enhancement-mode n-type HEMT coupled between the first output terminal and the power supply reference node,

the depletion-mode n-type HEMT is configured as a diode, and

the enhancement-mode n-type HEMT comprises a gate coupled to the first node.

5. The circuit of claim 1 , wherein

the third series of n-type HEMTs comprises:

a depletion-mode n-type HEMT and a first enhancement-mode n-type HEMT coupled between the power supply node and the second node; and

a second enhancement-mode n-type HEMT coupled between the second node and the power supply reference node,

the depletion-mode n-type HEMT is configured as a diode,

the first enhancement-mode n-type HEMT comprises a gate coupled to the first output terminal, and

the second enhancement-mode n-type HEMT comprises a gate configured to receive the input signal.

6. The circuit of claim 1 , wherein

the fourth series of n-type HEMTs comprises:

a first enhancement-mode n-type HEMT, a fourth node, and a depletion-mode n-type HEMT coupled between the power supply node and the third node; and

a second enhancement-mode n-type HEMT coupled between the third node and the power supply reference node,

each of the first enhancement-mode n-type HEMT and the depletion-mode n-type HEMT is configured as a diode, and

the second enhancement-mode n-type HEMT comprises a gate coupled to the third node.

7. The circuit of claim 6 , further comprising:

a capacitive device coupled between the fourth node and the second output terminal.

8. The circuit of claim 1 , wherein

the fifth series of n-type HEMTs comprises:

a first enhancement-mode n-type HEMT coupled between the power supply node and the second output terminal; and

a second enhancement-mode n-type HEMT coupled between the second output terminal and the power supply reference node,

the first enhancement-mode n-type HEMT comprises a gate coupled to the third node, and

the second enhancement-mode n-type HEMT comprises a gate coupled to the second node.

9. The circuit of claim 1 , wherein

the power supply node is configured to receive a power supply voltage level from a battery.

10. An integrated circuit (IC) comprising: first and second power supply nodes; a power supply reference node; a protection circuit comprising a first output terminal and first and second series of n-type high electron mobility transistors (HEMTs) coupled between the first power supply node and the power supply reference node; a gate driver comprising a second output terminal and third through fifth series of n-type HEMTs coupled between the first power supply node and the power supply reference node; and an n-type HEMT switching device coupled between the second power supply node and the power supply reference node, wherein the first series of n-type HEMTs is configured to control a first voltage on a first node responsive to a first power supply voltage on the first power supply node, the second series of n-type HEMTs is configured to control a second voltage on the first output terminal responsive to the first voltage, the third series of n-type HEMTs is configured to control an internal signal on a second node responsive to the second voltage and to an input signal, the fourth series of n-type HEMTs is configured to control a third voltage on a third node responsive to the internal signal, the fifth series of n-type HEMTs is configured to control an output signal at the second output terminal responsive to the internal signal and the third voltage, and the n-type HEMT switching device is configured to couple a first sub-circuit to one of the second power supply node, the power supply reference node, or a second sub-circuit responsive to the output signal.

11. The IC of claim 10 , wherein

the protection circuit further comprises a voltage divider configured to generate a fourth voltage based on the power supply voltage,

the first series of n-type HEMTs comprises a first depletion-mode n-type HEMT coupled between the power supply node and the first node and a first enhancement-mode n-type HEMT coupled between the first node and the power supply reference node,

the second series of n-type HEMTs comprises a second depletion-mode n-type HEMT coupled between the power supply node and the first output terminal and a second enhancement-mode n-type HEMT coupled between the first output terminal and the power supply reference node,

each of the first and second depletion-mode n-type HEMTs is configured as a diode,

the first enhancement-mode n-type HEMT comprises a gate configured to receive the fourth voltage, and

the second enhancement-mode n-type HEMT comprises a gate coupled to the first node.

12. The IC of claim 11 , wherein

the voltage divider comprises:

a series of voltage divider components coupled between the power supply node and the power supply reference node; and

a third enhancement-mode n-type HEMT arranged in parallel with a first voltage divider component of the series of voltage divider components,

wherein

the series of voltage divider components comprises a voltage tap coupled to the gate of the first enhancement-mode n-type HEMT, and

the third enhancement-mode n-type HEMT comprises a gate coupled to the first node.

13. The IC of claim 10 , wherein

the fourth series of n-type HEMTs comprises:

a first enhancement-mode n-type HEMT, a fourth node, and a depletion-mode n-type HEMT coupled between the power supply node and the third node; and

a second enhancement-mode n-type HEMT coupled between the third node and the power supply reference node,

each of the first enhancement-mode n-type HEMT and the depletion-mode n-type HEMT is configured as a diode,

the second enhancement-mode n-type HEMT comprises a gate coupled to the third node, and

the circuit further comprises a capacitive device coupled between the fourth node and the second output terminal.

14. The IC of claim 10 , wherein the n-type HEMT switching device comprises a gate coupled to the second output terminal.

15. The IC of claim 10 , wherein

the first sub-circuit comprises some or all of a power or voltage conversion circuit or a power or voltage regulation circuit.

16. The IC of claim 10 , wherein the gate driver is positioned between the protection circuit and the n-type HEMT switching device and adjacent to each of the protection circuit and the n-type HEMT switching device.

17. A method of operating a driver circuit, the method comprising:

receiving a first power supply voltage on a first power supply node;

in response to the first power supply voltage, using a first series of n-type high electron mobility transistors (HEMTs) coupled between the power supply node and a power supply reference node to control a first voltage on a first node;

in response to the first voltage, using a second series of n-type HEMTs coupled between the power supply node and the power supply reference node to control a second voltage on a first output terminal;

in response to the second voltage and an input signal, using a third series of n-type HEMTs coupled between the power supply node and the power supply reference node to control an internal signal on a second node;

in response to the internal signal, using a fourth series of n-type HEMTs coupled between the power supply node and the power supply reference node to control a third voltage on a third node; and

in response to the internal signal and the third voltage, using a fifth series of n-type HEMTs coupled between the power supply node and the power supply reference node to control an output signal at a second output terminal.

18. The method of claim 17 , wherein

the receiving the first power supply voltage on the first power supply node comprises receiving the first power supply voltage from a battery.

19. The method of claim 17 , wherein

the using the fifth series of n-type HEMTs to control the output signal at the second output terminal comprises using a capacitive device coupled between the fourth series of n-type HEMTs and the second output terminal.

20. The method of claim 17 , further comprising: in response to the output signal, using an n-type HEMT switching device to couple a first sub-circuit to one of the power supply reference node, a second sub-circuit, or a second power supply node configured to receive a second power supply voltage greater than the first power supply voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2023
From: TSAI, MING HSIEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 063538/0915 →
Continuity (4)
Continuation 17396515 · Aug 6, 2021
Continuation 16450544 · Jun 24, 2019
Provisional Application 62712961 · Jul 31, 2018
Related Publication 20230275575A1 · Aug 31, 2023