Method and systems for creating electronic devices via maskless lithography
A method includes generating pattern data including common chip design data and one or more bit spaces or place holders reserved for non-common chip design data or information related to the non-common chip design data. The method includes introducing the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the pattern data before streaming the pattern data to the maskless pattern writer. The common chip design data defines a common design layout part of an electronic device to be created on a wafer using the maskless pattern writer. The non-common chip design data defines a non-common design layout part of the electronic device to be created on the wafer using the maskless pattern writer, the non-common design layout part being different from other electronic devices created on the wafer.
1 . A method of creating electronic devices using a maskless lithographic exposure system comprising a maskless pattern writer, the method comprising:
generating pattern data comprising common chip design data and one or more bit spaces or place holders reserved for non-common chip design data or information related to the non-common chip design data to be inserted after the generating; and
introducing the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the pattern data before streaming the pattern data to the maskless pattern writer,
wherein the common chip design data defines a common design layout part of an electronic device to be created on a wafer using the maskless pattern writer under control of the pattern data, the common design layout part being identical to other electronic devices created on the wafer, and
wherein the non-common chip design data defines a non-common design layout part of the electronic device to be created on the wafer using the maskless pattern writer under control of the pattern data, the non-common design layout part being different from other electronic devices created on the wafer.
2 . The method of claim 1 , wherein introducing the non-common chip design data or the information related to the non-common chip design data into the one or more bit spaces or place holders of the pattern data is performed once for the entire wafer before streaming the pattern data for the wafer to the maskless pattern writer.
3 . The method of claim 2 , wherein the pattern data is in a vector format.
4 . The method of claim 1 , wherein introducing the non-common chip design data or the information related to the non-common chip design data into the one or more bit spaces or place holders of the pattern data is performed per electronic device before streaming the pattern data for the corresponding electronic device to the maskless pattern writer.
5 . The method of claim 4 , wherein the pattern data is in a bitmap format.
6 . The method of claim 1 , wherein the streaming is performed once per field or once per chip.
7 . The method of claim 1 , further comprising:
generating the non-common chip design data based on secret data received from a unique data generator included in the lithography exposure system.
8 . The method of claim 7 , wherein the secret data includes at least one of a secret key and a secret ID.
9 . The method of claim 7 , wherein the unique data generator receives the secret data from an external provider in an encrypted format.
10 . The method of claim 1 , further comprising:
receiving product identification information or serial number information related to a chip to be manufactured from a manufacturing database;
receiving batches of identification/key pairs from a key management service;
generating the non-common chip design data using the received product identification information or serial number information and the received identification/key pairs.
11 . The method of claim 1 , wherein the maskless lithographic exposure system comprises an input generator for inputting the non-common chip design data or the information related to the non-common chip design data to a process job generator of an execution system in an encrypted manner in a form of encrypted code, a machine control part of the maskless pattern writer converting the encrypted code by intermixing with the pattern data in an obfuscated manner.
12 . A maskless lithographic exposure system comprising:
a maskless pattern writer configured to receive pattern data and expose a pattern on a surface of a target using a charged particle beam and according to the pattern data obtained by:
generation of intermediate pattern data comprising common chip design data and one or more bit spaces or place holders reserved for non-common chip design data or information related to the non-common chip design data to be inserted after the generation, and
an insertion, by the maskless lithographic exposure system, of the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the intermediate pattern data before streaming the pattern data to the maskless pattern writer,
wherein the common chip design data defines a common design layout part of an electronic device to be created on a wafer using the maskless pattern writer under control of the pattern data, the common design layout part being identical to other electronic devices created on the wafer, and
wherein the non-common chip design data defines a non-common design layout part of said electronic device to be created on the wafer using the maskless pattern writer under control of the pattern data, the non-common design layout part being different from other electronic devices created on the wafer.
13 . The maskless lithographic exposure system of claim 12 , wherein the insertion, by the maskless lithographic exposure system, of the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the intermediate pattern data is performed once for the entire wafer before streaming the pattern data for the wafer to the maskless pattern writer.
14 . The maskless lithographic exposure system of claim 13 , wherein the intermediate pattern data is in a vector format.
15 . The maskless lithographic exposure system of claim 12 , wherein the insertion, by the maskless lithographic exposure system, of the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the intermediate pattern data is performed per electronic device before streaming the pattern data for the corresponding electronic device to the maskless pattern writer.
16 . The maskless lithographic exposure system of claim 15 , wherein the intermediate pattern data is in a bitmap format.
17 . A data processing system comprising:
a memory storing a set of instructions; and
one or more processors configured to execute the set of instructions to cause the data processing system to perform operations for generating pattern data, wherein the pattern data represents at least a part of one or more electronic devices, to be created under control of the pattern data using a maskless lithographic exposure system comprising a maskless pattern writer, the operations comprising:
generating intermediate pattern data comprising common chip design data and one or more bit spaces or place holders reserved for non-common chip design data or information related to the non-common chip design data to be inserted after the generating,
introducing the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the intermediate pattern data to obtain the pattern data before streaming the pattern data to the maskless pattern writer,
wherein the common chip design data defines a common design layout part of an electronic device to be created on a wafer using the maskless pattern writer under control of the pattern data, the common design layout part being identical to other electronic devices created on the wafer,
wherein the non-common chip design data defines a non-common design layout part of the electronic device to be created on the wafer using the maskless pattern writer under control of the pattern data, the non-common design layout part being different from other chips created on the wafer.
18 . The data processing system of claim 17 , wherein introducing the non-common chip of the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the intermediate pattern data is performed once for the entire wafer to obtain the pattern data for the wafer before streaming the pattern data to the maskless pattern writer.
19 . The data processing system of claim 17 , wherein introducing the non-common chip of the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the intermediate pattern data is performed per electronic device to obtain the pattern data for the corresponding electronic device before streaming the pattern data to the maskless pattern writer.
20 . The data processing system of claim 17 , wherein the streaming is performed once per field or once per chip.