Memory device containing TSG deck and method of forming the same
Memory device, memory system and formation method are provided. The method includes forming a sacrificial layer over a dielectric-pair stack, the sacrificial layer containing a top selective gate (TSG) cut structure over the dielectric-pair stack; forming a channel plug structure including a lower plug portion in the dielectric-pair stack and an upper plug portion through the sacrificial layer; forming a barrier layer at least enveloping the upper plug portion of the channel plug structure after a removal of the sacrificial layer; and forming a semiconductor layer over the dielectric-pair stack to embed the TSG cut structure, the barrier layer, and the upper plug portion of the channel plug structure.
1 . A memory device comprising:
a stack structure;
a semiconductor layer over the stack structure and containing a top selective gate (TSG) cut structure;
a channel plug structure passing through the semiconductor layer, and penetrating into the stack structure under the semiconductor layer and in contact with a channel layer extending through the stack structure; and
a barrier layer including at least a portion formed at a bottom surface of the semiconductor layer above the channel layer.
2 . The memory device according to claim 1 , wherein
the channel plug structure further includes an upper plug portion in the semiconductor layer and a lower plug portion in the stack structure, and
at an interface between the upper and lower plug portions of the channel plug structure, the upper plug portion includes a width less than the lower plug portion.
3 . The memory device according to claim 2 , wherein
the barrier layer is further formed between the lower plug portion and the semiconductor layer.
4 . The memory device according to claim 1 , wherein
a top surface of the channel plug structure and a top surface of the semiconductor layer are coplanar with each other.
5 . The memory device according to claim 1 , wherein
the barrier layer further comprises a portion through the semiconductor layer, and between the semiconductor layer and an upper plug portion of the channel plug structure along a lateral direction of the semiconductor layer.
6 . The memory device according to claim 1 , wherein
the channel plug structure includes a lower plug portion, the lower plug portion including a sidewall surrounded by the channel layer; and
the barrier layer is further formed on a top surface of the channel layer.
7 . The memory device according to claim 1 , further comprising:
a channel structure extending through the stack structure and comprising a functional layer between the channel layer and the stack structure, the functional layer comprising:
a tunneling layer adjacent to the channel layer, a blocking layer adjacent to the stack structure, and a charge trap layer between the blocking layer and the tunneling layer, wherein
a lower plug portion of the channel plug structure is formed above the channel layer and the tunneling layer, and further surrounded by the charge trap layer.
8 . The memory device according to claim 1 , wherein
the stack structure comprises a dielectric-pair stack or a layer stack comprising alternating layers of a conductor layer and a dielectric layer.
9 . A memory system comprising:
a controller, and
a memory device comprising:
a stack structure;
a semiconductor layer over the stack structure and containing a top selective gate (TSG) cut structure;
a channel plug structure passing through the semiconductor layer, and penetrating into the stack structure under the semiconductor layer and in contact with a channel layer extending through the stack structure; and
a barrier layer including at least a portion formed at a bottom surface of the semiconductor layer above the channel layer.