Semiconductor device with germanium-based channel
A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first dielectric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.
1 . A method, comprising:
forming a germanium-based channel material over a substrate;
forming a germanium oxide interfacial layer over the germanium-based channel material;
forming a germanium oxynitride layer over the germanium oxide interfacial layer;
forming a high-k dielectric layer over the germanium oxynitride layer; and
forming a gate metal layer over the high-k dielectric layer.
2 . The method of claim 1 , wherein the germanium oxynitride layer is formed by nitridating a surface layer of the germanium oxide interfacial layer.
3 . The method of claim 1 , further comprising:
performing an annealing process on the germanium oxynitride layer.
4 . The method of claim 3 , wherein the annealing process is performed at a temperature lower than about 500° C.
5 . The method of claim 3 , wherein the annealing process is performed such that a thickness of the germanium oxynitride layer is reduced.
6 . The method of claim 3 , wherein the annealing process is performed before forming the high-k dielectric layer over the germanium oxynitride layer.
7 . The method of claim 1 , wherein the germanium oxide interfacial layer is formed by performing an oxidation process on the germanium-based channel material.
8 . A method, comprising:
forming a plurality of first transistors over a substrate;
forming a first bonding dielectric layer over the plurality of first transistors;
bonding a multi-layer stack to the first bonding dielectric layer using a second bonding dielectric layer, the multi-layer stack comprising alternating first semiconductor layers and second semiconductor layers; and
replacing first portions of the first semiconductor layers with a gate structure, the gate structure comprising:
a germanium oxide layer interfacing one of the second semiconductor layer;
a germanium oxynitride layer interfacing the germanium oxide layer;
a high-k dielectric layer over the germanium oxynitride layer; and
a gate metal layer over the high-k dielectric layer.
9 . The method of claim 8 , wherein the germanium oxynitride layer has a nitrogen concentration gradient.
10 . The method of claim 8 , further comprising:
removing second portions of the first semiconductor layers to form source/drain recesses; and
forming epitaxial source/drain regions in the source/drain recesses.
11 . The method of claim 10 , wherein the first transistors are of a first conductivity type, and the epitaxial source/drain regions are of a second conductivity type different from the first conductivity type.
12 . The method of claim 8 , wherein the second semiconductor layers are germanium-containing semiconductor layers.
13 . The method of claim 8 , wherein the high-k dielectric layer is in contact with the germanium oxynitride layer.
14 . The method of claim 8 , wherein the germanium oxynitride layer is formed by performing a nitridation process on the germanium oxide layer.
15 . The method of claim 8 , wherein the germanium oxide layer is formed by performing an oxidation process on the second semiconductor layers.
16 . An integrated circuit (IC) structure, comprising:
a first transistor comprising a first channel region and a first gate structure over the first channel region; and
a second transistor stacked over the first transistor, the second transistor comprising a second channel region and a second gate structure over the second channel region, the second gate structure comprising:
a germanium oxide layer over the second channel region;
a high-k dielectric layer over the germanium oxide layer;
a gate metal layer over the high-k dielectric layer; and
a nitrogen-containing layer spacing apart the germanium oxide layer from the high-k dielectric layer.
17 . The IC structure of claim 16 , wherein the nitrogen-containing layer comprises germanium oxynitride.
18 . The IC structure of claim 16 , wherein the nitrogen-containing layer has a non-uniform nitrogen concentration.
19 . The IC structure of claim 16 , wherein the nitrogen-containing layer has a nitrogen concentration changing as a function of thickness of the nitrogen-containing layer.
20 . The IC structure of claim 16 , wherein the first transistor and the second transistor are of different conductivity types.