Granted Patent B2

US 12,660,612 · App. 18/326,055 · Granted Jun 16, 2026

Inventors: Huimei Zhou (Albany, NY); Yoo-Mi Lee (Montvale, NJ); Ruilong Xie (Niskayuna, NY)

Assignee: International Business Machines Corporation

H10W20/496H10D62/118H10W20/42H10W20/427

Abstract

Claims (26)

1 . A semiconductor structure comprising:

an array of transistors;

a backside power rail, wherein the backside power rail directly contacts a bottommost surface of a shallow trench isolation region; and

a metal-insulator-metal (MIM) capacitor embedded in a backside power delivery network beneath the array of transistors, wherein the MIM capacitor directly contacts a bottommost surface of the backside power rail.

2 . The semiconductor structure according to claim 1 , further comprising:

a first via electrically connecting a source drain contact to the backside power delivery network; and

a second via electrically connecting frontside wiring to the backside power delivery network.

3 . The semiconductor structure according to claim 1 , wherein the backside power delivery network and a metal layer of the MIM capacitor are embedded in a backside dielectric layer.

4 . The semiconductor structure according to claim 1 , wherein a metal layer of the MIM capacitor directly contacts the backside power delivery network in a region directly below a gate.

5 . The semiconductor structure according to claim 1 , wherein a backside dielectric layer physically separates a metal layer of the MIM capacitor from the backside power delivery network in a region directly below a source drain region of at least one transistor of the array of transistors.

6 . The semiconductor structure according to claim 1 , further comprising:

backside wiring in direct contact with a metal layer of the MIM capacitor.

7 . The semiconductor structure according to claim 1 , wherein the array of transistors comprises an array of nanosheet transistors.

8 . A semiconductor structure comprising:

an array of transistors;

a backside power rail; and

a metal-insulator-metal (MIM) capacitor beneath the array of transistors, wherein a metal layer of the MIM capacitor directly contacts the backside power rail.

9 . The semiconductor structure according to claim 8 , further comprising:

a first via electrically connecting a source drain contact to a backside power delivery network; and

a second via electrically connecting frontside wiring to the backside power rail.

10 . The semiconductor structure according to claim 8 , wherein the backside power rail and the metal layer of the MIM capacitor are embedded in a backside dielectric layer.

11 . The semiconductor structure according to claim 8 , wherein a metal layer of the MIM capacitor directly contacts a backside power delivery network in a region directly below a gate.

12 . The semiconductor structure according to claim 8 , wherein a backside dielectric layer physically separates the metal layer of the MIM capacitor from a backside power delivery network in a region directly below a source drain region of at least one transistor of the array of transistors.

13 . The semiconductor structure according to claim 8 , further comprising:

backside wiring in direct contact with the metal layer of the MIM capacitor.

14 . The semiconductor structure according to claim 8 , wherein the array of transistors comprises an array of nanosheet transistors.

Assignments (1)

Continuity (1)

References Cited (13)