Direct N/P local interconnect
Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.
1 . A device, comprising:
a shallow trench isolation (STI) oxide formed on a substrate;
an N contact formed within the STI oxide and on the substrate on a first side of the device;
an N source/drain formed on the N contact;
a P contact formed within the STI oxide and on the substrate on a second side of the device;
a P source/drain formed on the P contact; and
a local interconnect formed on and in contact with the STI oxide, the N source/drain, and the P source/drain, the local interconnect electrically coupling the N source/drain and the P source/drain,
wherein a local interconnect recess depth is less than a local interconnect N depth, or the local interconnect recess depth is less than a local interconnect P depth, or both,
the local interconnect N depth being a depth of a first region of the local interconnect above the N contact,
the local interconnect P depth being a depth of a second region of the local interconnect above the P contact, and
the local interconnect recess depth being a depth of a recess region of the local interconnect in between the first and second regions.
2 . The device of claim 1 , wherein the local interconnect is formed from any one or more of tungsten (W), cobalt (Co), ruthenium (Ru), nickel (Ni), and niobium (Nb).
3 . The device of claim 1 ,
wherein a lower surface of the local interconnect in the recess region is higher than a highest point of the N source/drain,
wherein the lower surface of the local interconnect in the recess region is higher than a highest point of the P source/drain, or
both.
4 . The device of claim 1 , further comprising:
an etch stop layer formed between the local interconnect and the STI oxide in the recess region,
wherein there is no etch stop layer between the local interconnect and the STI oxide in the first region or there is no etch stop layer between the local interconnect and the STI oxide in the second region or both.
5 . The device of claim 4 , wherein the etch stop layer is ‘U’ shaped.
6 . The device of claim 4 , wherein the etch stop layer is formed from any one or more of silicon nitride (SiN), silicon carbon nitride (SiCN), aluminum nitride (AlN), and aluminum oxide (Al 2 O 3 ).
7 . The device of claim 1 , further comprising:
a low-k dielectric formed between the local interconnect and the substrate in the recess region.
8 . The device of claim 7 ,
wherein the STI oxide is formed on the substrate in the recess region, and
wherein the low-k dielectric is formed on the STI oxide in the recess region.
9 . The device of claim 7 , wherein the low-k dielectric is formed directly on the substrate in the recess region.
10 . The device of claim 7 , further comprising:
an etch stop layer formed between the local interconnect and the low-k dielectric in the recess region.
11 . The device of claim 1 , wherein the device is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.
12 . A method of fabricating a device, the method comprising:
forming a shallow trench isolation (STI) oxide on a substrate;
forming an N contact within the STI oxide and on the substrate on a first side of the device;
forming an N source/drain on the N contact;
forming a P contact within the STI oxide and on the substrate on a second side of the device;
forming a P source/drain on the P contact; and
forming a local interconnect on and in contact with the STI oxide, the N source/drain, and the P source/drain, the local interconnect electrically coupling the N source/drain and the P source/drain,
wherein a local interconnect recess depth is less than a local interconnect N depth, or the local interconnect recess depth is less than a local interconnect P depth, or both,
the local interconnect N depth being a depth of a first region of the local interconnect above the N contact,
the local interconnect P depth being a depth of a second region of the local interconnect above the P contact, and
the local interconnect recess depth being a depth of a recess region of the local interconnect in between the first and second regions.
13 . The method of claim 12 , wherein the local interconnect is formed from any one or more of tungsten (W), cobalt (Co), ruthenium (Ru), nickel (Ni), and niobium (Nb).
14 . The method of claim 12 ,
wherein a lower surface of the local interconnect in the recess region is higher than a highest point of the N source/drain,
wherein the lower surface of the local interconnect in the recess region is higher than a highest point of the P source/drain, or
both.
15 . The method of claim 12 , further comprising:
forming an etch stop layer between the local interconnect and the STI oxide in the recess region,
wherein there is no etch stop layer between the local interconnect and the STI oxide in the first region or there is no etch stop layer between the local interconnect and the STI oxide in the second region or both.
16 . The method of claim 15 , wherein the etch stop layer is ‘U’ shaped.
17 . The method of claim 15 , wherein the etch stop layer is formed from any one or more of silicon nitride (SiN), silicon carbon nitride (SiCN), aluminum nitride (AlN), and aluminum oxide (Al 2 O 3 ).
18 . The method of claim 12 , further comprising:
forming a low-k dielectric between the local interconnect and the substrate in the recess region.
19 . The method of claim 18 ,
wherein the STI oxide is formed on the substrate in the recess region, and
wherein the low-k dielectric is formed on the STI oxide in the recess region.
20 . The method of claim 18 , wherein the low-k dielectric is formed directly on the substrate in the recess region.
21 . The method of claim 18 , further comprising:
forming an etch stop layer between the local interconnect and the low-k dielectric in the recess region.