Dynamic random access memory and manufacturing method thereof
Provided are a dynamic random access memory and a method for manufacturing the same. The DRAM includes: a plurality of word line structures, located in a substrate; a plurality of bit line structures, located above the substrate, crossing over the plurality of word line structures; a plurality of node contacts, each of which being located between adjacent two of the word line structures and adjacent two of the bit line structures; and a plurality of first spacers, separating the plurality of node contacts. Each of the plurality of first spacers further comprises: spacer material, filled in a gap between the node contacts that are adjacent; and a first cap layer, embedded in the spacer material.
1 . A dynamic random access memory comprising:
a plurality of word line structures, located in a substrate;
a plurality of bit line structures, located over the substrate, spanning over the plurality of word line structures;
a plurality of node contacts, each of which being located between adjacent two of the word line structures and adjacent two of the bit line structures;
a plurality of first spacers, separating the plurality of node contacts,
wherein each of the plurality of first spacers further comprises:
spacer material, filled in a gap between the node contacts that are adjacent; and
a first cap layer, embedded in the spacer material; and
a plurality of second spacers, located on a plurality of sidewalls of the plurality of bit line structures,
wherein each of the plurality of second spacers comprises:
an inner liner layer, located on a sidewall of the corresponding bit line structure;
a middle liner layer, located on a lower sidewall of the inner liner layer;
a second cap layer, located on an upper sidewall of the inner liner layer; and
an outer liner layer, wherein the middle liner layer and the second cap layer are sandwiched between the inner liner layer and the outer liner layer.
2 . The dynamic random access memory according to claim 1 , wherein the spacer material comprises:
a main portion; and
an extension portion, located on the main portion and connected to the main portion, wherein the first cap layer is located in the extension portion.
3 . The dynamic random access memory according to claim 1 , wherein a seam is provided between the spacer material and the first cap layer.
4 . The dynamic random access memory according to claim 3 , wherein the seam has an irregular shape.
5 . The dynamic random access memory according to claim 3 , wherein the seam is higher than the plurality of node contacts.
6 . The dynamic random access memory according to claim 1 , wherein a material of the first cap layer comprises silicon nitride.
7 . The dynamic random access memory according to claim 1 , further comprising:
a plurality of dielectric pillars, arranged on an isolation structure at an end region of the substrate, the end region being adjacent to a memory cell region;
a plurality of third spacers, arranged on sidewalls of the plurality of dielectric pillars;
a plurality of third cap layers, located on the plurality of dielectric pillars; and
a plurality of fourth cap layers, embedded in the plurality of third spacers.
8 . A method for manufacturing the dynamic random access memory of claim 1 , comprising:
forming the plurality of word line structures in the substrate;
forming the plurality of bit line structures above the substrate;
forming a plurality of node contact materials, wherein each of the plurality of node contact material is located between adjacent two of the word line structures and adjacent two of the bit line structures;
forming the plurality of spacer materials between the plurality of node contact materials, wherein the plurality of spacer materials have a plurality of seams;
performing a removal step to remove a portion of the plurality of spacer materials to expose the plurality of seams;
forming the plurality of first cap layers in the plurality of seams, wherein the remained plurality of spacer materials forms a plurality of first spacers, and the plurality of first cap layers are embedded in the plurality of first spacers; and
removing a portion of the plurality of node contact materials to form the plurality of node contacts.
9 . The method according to claim 8 , wherein a material of the plurality of first layers comprises silicon nitride.
10 . The method according to claim 8 , wherein forming the plurality of first cap layers comprises:
forming cap materials on the plurality of node contact materials and the plurality of bit line structures, and filling in the plurality of seams; and
removing a portion of the cap materials to form the plurality of first cap layers.
11 . The method according to claim 10 , wherein the plurality of first cover materials are not fully filled in the plurality of seams.
12 . The method according to claim 10 , further comprising:
forming a plurality of second spacers on a plurality of sidewalls of the plurality of bit line structures,
wherein each of the second spacers comprises:
an inner liner layer, located on a sidewall of a corresponding bit line structure,
a middle liner layer, located on a sidewall of the inner lining layer, and
an outer liner layer, wherein the middle liner layer is sandwiched between the inner liner layer and outer liner layer.
13 . The method according to claim 12 , wherein the removal step further comprises:
removing a portion of the plurality of second spacers.
14 . The method according to claim 13 , further comprising:
removing a portion of the middle liner layer to form a groove; and
forming a second cap layer in the groove.
15 . The method according to claim 14 , wherein the cap material is also filled into the groove to form the second cap layer.