Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell
Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells and divided into a first region and a second region, and a sensing circuit that generates a first read current for determining data stored in memory cells belonging to the first region from among the plurality of memory cells wherein the second region configured to store a value of the first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a memory cell where the data is stored and a value of an initial read current applied to the memory cell.
1 . A memory device comprising:
a memory cell array including a plurality of memory cells and divided into a first region and a second region;
a sensing circuit configured to generate a first read current for determining data stored in memory cells belonging to the first region from among the plurality of memory cells,
a voltage generator configured to generate a code value; and
a write driver configured to perform a program operation on the first region based on the code value,
wherein the second region is configured to store
a value of the first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a memory cell where the data is stored, and
a value of an initial read current applied to the memory cell, and wherein the write driver includes
first-type transistors each including a first end connected with a first power supply voltage and a second end connected with an output node, and
second-type transistors each including a first end connected with a second power supply voltage and a second end connected with the output node.
2 . The memory device of claim 1 , wherein each of the plurality of memory cells includes:
a cell transistor including a first end connected with a source line, and a gate electrode connected with a word line; and
a magnetic tunneling junction element including a first end connected with a second end of the cell transistor and a second end connected with a bit line.
3 . The memory device of claim 1 , wherein the sensing circuit includes:
a first current source configured to generate the first read current;
a second current source configured to generate a second read current; and
a sense amplifier configured to amplify a difference between a voltage drop at a first node according to an application of the first read current to a first bit line connected with a selected memory cell and a voltage drop at a second node according to an application of the second read current to a reference bit line.
4 . The memory device of claim 3 , wherein a resistance having the value of the reference resistance is connected with the reference bit line.
5 . The memory device of claim 4 , wherein the resistance having the value of the reference resistance and a gate electrode of a transistor constituting the memory cell array are implemented with poly silicon.
6 . The memory device of claim 3 , wherein at least one dummy memory cell being identical in structure to the selected memory cell is connected with the reference bit line.
7 . The memory device of claim 1 , wherein
the code value includes a first code value and a second code value,
the first-type transistors are configured to receive corresponding bits of the first code value from the voltage generator, respectively, and
the second-type transistors are configured to receive corresponding bits of the second code value from the voltage generator, respectively.
8 . The memory device of claim 1 , wherein the second region is implemented with an anti-fuse cell array.
9 . A memory device comprising:
a memory cell array including a first region configured to store data and a second region configured to store a current value;
a column decoder configured to select a bit line connected with a memory cell selected from memory cells of the first region;
a row decoder configured to drive a word line connected with the selected memory cell; and
a sensing circuit configured to generate a first read current based on the current value to determine data stored in a memory cell of the first region,
wherein the current value is determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of the memory cell where the data is stored and a value of an initial read current applied to the memory cell, and
wherein the value of the reference resistance is determined based on a first result of counting a number of fail bits of the first region programmed to the parallel state for each resistance value and a second result of counting a number of fail bits of the first region programmed to the anti-parallel state for each resistance value.
10 . The memory device of claim 9 , wherein each of the memory cells of the first region includes:
a cell transistor including a first end connected with a source line and a gate electrode connected with a word line; and
a magnetic tunneling junction element including a first end connected with a second end of the cell transistor and a second end connected with a bit line.
11 . The memory device of claim 9 , wherein the sensing circuit includes:
a first current source configured to generate the first read current;
a second current source configured to generate a second read current; and
a sense amplifier configured to amplify a difference between a voltage drop at a first node according to an application of the first read current to a bit line connected with the selected memory cell and a voltage drop at a second node according to an application of the second read current to a reference bit line.
12 . The memory device of claim 9 , further comprising:
a voltage generator configured to generate a code value; and
a write driver configured to perform a program operation on the first region based on the code value,
wherein the write driver, includes
first-type transistors each including a first end connected with a first power supply voltage and a second end connected with an output node, and
second-type transistors each including a first end connected with a second power supply voltage and a second end connected with the output node.
13 . The memory device of claim 12 , wherein
the code value includes a first code value and a second code value,
the first-type transistors are configured to receive corresponding bits of the first code value from the voltage generator, respectively, and
the second-type transistors are configured to receive corresponding bits of the second code value from the voltage generator, respectively.