Signal processing apparatus and non-transitory computer-readable storage medium
This invention provides a signal processing apparatus which comprises a CPU and a programmable signal processor which has a plurality of execution units, a register file having a plurality of registers connected serially, and a shift controller which issues a shift signal to shift data held in the register file when each of the execution units has completed execution of a program of one cycle. Each of the execution units, after the execution of the program of one cycle, re-executes the program in accordance with the reception of the shift signal. The CPU stores, to a program memory in each of the execution units, a program including instructions to store data of a result of processing to one of registers so that the other execution unit refers the data in next cycle.
1. A signal processing apparatus comprising:
a central processing unit (CPU); and
a programmable signal processing circuit having the following:
a plurality of execution circuits each of which has a program memory and executes a program stored in the program memory,
wherein the plurality of execution circuits can operate in parallel;
a register file used for the plurality of execution circuits,
wherein the register file has a plurality of registers serially connected and transfers, in accordance with a shift signal, data held by each of the plurality of registers to a register located downstream;
a shift controller that issues the shift signal to the plurality of execution circuits at a timing at which the plurality of execution circuits do not execute the program,
wherein the CPU stores, to each program memory of the plurality of execution circuits, a program including instructions to make a register of the register file located upstream of a register that a second execution circuit of the plurality of execution circuits is to reference in order to input data be a storage destination for data of a result by execution of the program by a first execution circuit of the plurality of execution circuits so that the data of the result by the execution of the program by the first execution circuit is transferred to the second execution circuit via the register file.
2. The signal processing apparatus according to claim 1 , wherein the shift controller issues the shift signal to the plurality of execution circuits in a case where each of the plurality of execution circuits has completed execution of one cycle of the program.
3. The signal processing apparatus according to claim 2 , wherein each of the plurality of execution circuits stops executing the program in a case where each of the plurality of execution circuits has completed execution of one cycle of the program and executes the program again in accordance with the shift signal.
4. The signal processing apparatus according to claim 2 , wherein each of the execution circuits has a program counter and a detector that detects an instruction indicating an end of one cycle of the program,
wherein the program counter stops updating a count value in accordance with a detection signal from the detector and sets a head address of the program to the program counter, and
wherein the shift controller issues the shift signal in a case where the shift controller has received the detection signals from the detectors of all of the plurality of execution circuits.
5. The signal processing apparatus according to claim 1 , wherein the execution circuit includes a setting circuit that sets data to be processed to the register,
wherein the programmable signal processing circuit has a reading circuit that has a program memory,
wherein the reading circuit, by executing a program stored in the program memory of the reading circuit, reads the data to be processed from an external memory and outputs the read data to the setting circuit, and
the CPU stores a program for specifying the data to be processed to the program memory of the reading circuit.
6. The signal processing apparatus according to claim 5 , wherein the reading circuit outputs the data to be processed to the setting circuit via a FIFO memory, and
wherein the reading circuit, in a case where the FIFO memory has become full, stops reading the data to be processed from the external memory, and in a case where free space has been generated in the FIFO memory, resumes reading.
7. The signal processing apparatus according to claim 1 , wherein the register files has an output register that stores data of a result of a predetermined process by the programmable signal processing circuit, and
wherein the CPU stores, to the program memory of an execution circuit that outputs the data of a result of a predetermined process among the plurality of execution circuit, a program including an instruction for storing data obtained by executing the program.
8. The signal processing apparatus according to claim 1 , wherein the program memory of each of the plurality of execution circuits and each register of the register file are mapped to different address spaces in a memory space of a predetermined IO bus.
9. The signal processing apparatus according to claim 1 , wherein the register file has a plurality of general-purpose registers that hold data unrelated to the shift signal,
wherein the programmable signal processing circuit shifts to a suspended state and an interrupt signal is output to an outside in a case where a predetermined value is stored in a predetermined one of the plurality of general-purpose registers.
10. The signal processing apparatus according to claim 1 , wherein the register file has a plurality of general-purpose registers that hold data unrelated to the shift signal,
wherein the CPU sets a predetermined value on the general-purpose resister and stores a program including an instruction for using the general-purpose resister to the program memory of the plurality of execution circuits.
11. The signal processing apparatus according to claim 1 , wherein the CPU reads the program executed by each of the plurality of execution circuits from a memory, and stores the read program to the program memory of each of the plurality of execution circuits.
12. The signal processing apparatus according to claim 11 , wherein the CPU executes the program stored in the memory and controls the image processing apparatus.
13. A non-transitory computer-readable storage medium storing programs to be executed by a signal processing apparatus comprising:
a central processing unit (CPU); and
a programmable signal processing circuit having the following:
a plurality of execution circuits each of which has a program memory and executes a program stored in the program memory,
wherein the plurality of execution circuits can operate in parallel;
a register file used for the plurality of execution circuits,
wherein the register file has a plurality of registers serially connected and transfers, in accordance with a shift signal, data held by each of the plurality of registers to a register located downstream;
a shift controller that issues the shift signal to the plurality of execution circuits at a timing at which the plurality of execution circuits do not execute the program,
wherein the program stored in the storage medium causes the CPU to store, to each program memory of the plurality of execution circuits, a program including instructions to make a register of the register file located upstream of a register that a second execution circuit of the plurality of execution circuits is to reference in order to input data be a storage destination for data of a result by execution of the program by a first execution circuit of the plurality of execution circuits so that the data of the result by the execution of the program by the first execution circuit is transferred to the second execution circuit via the register file.
14. The signal processing apparatus according to claim 1 , wherein
the signal processing apparatus is an image capturing apparatus, and
wherein the programmable signal processing circuit processes an image signal.