IP Library › Granted Patent US 12,621,238
Granted Patent B2
US 12,621,238 · App. 18/335,062 · Granted May 5, 2026

Network-on-chip packetization and routing method and apparatus for scalable high-performance networking on and off chip

Inventors: Chee Hak Teh (Bayan Lepas, MY); Yu Ying Ong (Bayan Lepas, MY); Soon Chieh Lim (Bayan Lepas, MY); Weng Li Leow (Bayan Lepas, MY); Yeong Tat Liew (Bayan Lepas, MY); Chuen Heong Khuan (Bayan Lepas, MY); Manobindra Gandhi (Bayan Lepas, MY); Muhamad Aidil Bin Jazmi (Bayan Lepas, MY)
Assignee: SKYECHIP BERHAD
H04L45/566H04L47/2458H04L49/25H04L49/9015
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Quick Facts
Patent No.
US 12,621,238
App. No.
18/335,062
Granted
May 5, 2026
Kind
B2
Abstract

The present invention discloses a computer-implemented method of data transmission for a Network-on-Chip to allow high performance routing through dynamic allocated buffer. The method comprises the steps of transferring command or data in a form of plurality of flits from a source node to a router and further to a destination node, and transmitting the flits from the destination node back to the router, wherein the flits are packetized for transmission according to channel width and transaction width, sequence, and priority routing through physical and virtual channels.

Claims (21)

1 . A computer-implemented method of data transmission for a Network-on-Chip, characterized in that said method comprises the steps of:

transferring command or data in a form of a plurality of flits from a source node to a router through one or more physical channels;

transmitting the flits from the router to a destination node through one or more physical channels by:

distributing the flits to a plurality of virtual channel First In First Out (FIFOs);

multiplexing the virtual channel FIFOs for flits entering the destination node;

spanning the flits into multiple flits if the physical channel that the virtual channel resides in has a channel width that is less than the transaction flit width, and incrementing the multiple flits until the end-of-packet before passing on to the next FIFO to a downstream destination node;

transmitting the flits from the destination node to the router through one or more physical channels by:

splitting the flits into multiple cycles based on the width of the physical channel that the flits are mapped to;

sending the flits according to the multiple cycles to the virtual channel;

selecting the virtual channel for sending the flits to the router via the physical channel;

wherein determining the flit sequence by linked-list management and priority routing.

2 . The computer-implemented method as claimed in claim 1 , wherein distributing the flits to the plurality of virtual channel First In First Out (FIFOs) based on each virtual channel FIFOs credit indication.

3 . The computer-implemented method as claimed in claim 1 , wherein the flits from the router to the destination node is transmitted as a request flit or a data flit.

4 . The computer-implemented method as claimed in claim 1 , wherein the flits from the destination node to the router is transmitted as a response flit or a data flit.

5 . The computer-implemented method as claimed in claim 1 , wherein selecting the virtual channel by arbitration for sending the flits to the router via the physical channel.

6 . The computer-implemented method as claimed in claim 1 , wherein the method further comprises generating variables by a linked-list manager to determine destination of the flits before transmitting the flits from the router to the destination node.

7 . The computer-implemented method as claimed in claim 6 , wherein creating a sequence of the flits forming a linked-list once the variables are generated.

8 . The computer-implemented method as claimed in claim 1 , wherein the priority routing comprising priority elevation of the flits in a linked-list when a higher priority flit is enqueued into the linked-list.

9 . An apparatus for data transmission for a Network-on-Chip, comprising:

a processor; and

a non-transitory computer readable medium comprising computer-executable instructions that, when executed by the processor, cause the apparatus to perform the method as claimed in claim 1 .

Assignments (3)
CHANGE OF NAME Recorded May 28, 2026
From: SKYECHIP SDN. BHD.
To: SKYECHIP BERHAD
Reel/Frame 075794/0806 →
CHANGE OF NAME Recorded Jan 3, 2026
From: SKYECHIP SDN. BHD.
To: SKYECHIP SDN. BHD.
Reel/Frame 074746/0464 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2023
From: TEH, CHEE HAK; ONG, YU YING; LIM, SOON CHIEH; LEOW, WENG LI; LIEW, YEONG TAT; KHUAN, CHUEN HEONG; GANDHI, MANOBINDRA; JAZMI, MUHAMAD AIDIL BIN
To: SKYECHIP SDN BHD
Reel/Frame 063953/0806 →
Priority Claims (1)
MY PI2023001073 · Mar 1, 2023 · national
Continuity (1)
Related Publication 20240297846A1 · Sep 5, 2024
References Cited (5)
US 8711867B2 · Guo et al. · 2014 [cited by applicant]
US 20250202834A1 · Jennings · 2025 [cited by examiner]
Kavya, K. et al. (“NOC linked-list based router for Packet Classification Application,” International Journal of Engineering Research & Technology (IJERT), vol. 9 Issue 07, Jul. 2020, ISSN: 2278-0181, published by http:… [cited by applicant]
Mello, A et al. “Virtual channels in networks on chip: Implementation and evaluation on hermes NOC,” 18th Symposium on Integrated Circuits and Systems Design, Pontificia Universidade Cat6lica do Rio Grande do Sul (FACIN… [cited by applicant]
Gharan, M.O. and Khan, G.N. “Packet-based adaptive virtual channel configuration for NOC systems,” 2014 International Workshop on the Design and Performance of Network on Chip (DPNoC 2014), Procedia Computer Science 34.… [cited by applicant]