Transformations in fused multiply-add instructions
Transformations in fused multiply-add instructions, including: receiving an extended fused multiply-add (FMA) instruction comprising: a first subset of bits corresponding to each operand of a fused multiply-add (FMA) operation, and a second subset of bits comprising an opcode for the extended FMA instruction, wherein the opcode identifies extended FMA instruction from an instruction set of a plurality of extended FMA instructions each having a different predefined opcode corresponding to a different combination of transformation-operand groupings; and performing, based on the opcode of the extended FMA instruction, the one or more transformations and the FMA operation.
1. A method comprising:
receiving an extended fused multiply-add (FMA) instruction comprising: a first subset of bits corresponding to each operand of a fused multiply-add (FMA) operation, and a second subset of bits comprising an opcode for the extended FMA instruction, wherein the opcode identifies extended FMA instruction from an instruction set of a plurality of extended FMA instructions each having a different predefined opcode corresponding to a different combination of transformation-operand groupings; and
performing, based on the opcode of the extended FMA instruction, the one or more transformations and the FMA operation.
2. The method of claim 1 , wherein the one or more transformations comprise a bit masking transformation.
3. The method of claim 1 , wherein the one or more transformations comprise a bit shifting operation.
4. The method of claim 1 , wherein the one or more transformations comprise a rounding operation.
5. The method of claim 1 , wherein the one or more transformations comprise a casting operation.
6. The method of claim 1 , wherein the one or more transformations comprise a conditional zeroing operation.
7. The method of claim 1 , wherein the first subset of bits indicates one or more registers storing one or more of the operands.
8. The method of claim 1 , wherein the first subset of bits indicates one or more of the operands.
9. An apparatus configured to perform steps comprising:
receiving an extended fused multiply-add (FMA) instruction comprising: a first subset of bits corresponding to each operand of a fused multiply-add (FMA) operation, and a second subset of bits comprising an opcode for the extended FMA instruction, wherein the opcode identifies extended FMA instruction from an instruction set of a plurality of extended FMA instructions each having a different predefined opcode corresponding to a different combination of transformation-operand groupings; and
performing, based on the opcode of the extended FMA instruction, the one or more transformations and the FMA operation.
10. The apparatus of claim 9 , wherein the one or more transformations comprise a bit masking transformation.
11. The apparatus of claim 9 , wherein the one or more transformations comprise a bit shifting operation.
12. The apparatus of claim 9 , wherein the one or more transformations comprise a rounding operation.
13. The apparatus of claim 9 , wherein the one or more transformations comprise a casting operation.
14. The apparatus of claim 9 , wherein the one or more transformations comprise a conditional zeroing operation.
15. The apparatus of claim 9 , wherein the first subset of bits indicates one or more registers storing one or more of the operands.
16. The apparatus of claim 9 , wherein the first subset of bits indicates one or more of the operands.
17. A computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer system to perform steps comprising:
receiving an extended fused multiply-add (FMA) instruction comprising: a first subset of bits corresponding to each operand of a fused multiply-add (FMA) operation, and a second subset of bits comprising an opcode for the extended FMA instruction, wherein the opcode identifies extended FMA instruction from an instruction set of a plurality of extended FMA instructions each having a different predefined opcode corresponding to a different combination of transformation-operand groupings; and
performing, based on the opcode of the extended FMA instruction, the one or more transformations and the FMA operation.
18. The computer program product of claim 17 , wherein the one or more transformations comprise a bit masking transformation.
19. The computer program product of claim 17 , wherein the one or more transformations comprise a bit shifting operation.
20. The computer program product of claim 17 , wherein the one or more transformations comprise a rounding operation.