Victim cache that supports draining write-miss entries
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
1. A device comprising:
a processor; and
a cache that includes:
a processor interface coupled to the processor;
a cache memory that includes:
a set of cache lines that includes a first cache line configurable to store a first write-miss entry; and
a set of line type entries that are each configured to store a respective value that specifies whether a respective line of the set of cache lines is associated with a write-miss entry; and
a controller coupled to the processor interface and to the cache memory and configured to:
detect a state of the processor interface; and
based on the state:
select the first cache line to evict based on the set of line type entries; and
evict the first cache line by providing a packet based on the first write-miss entry stored in the first cache line.
2. The device of claim 1 , wherein:
the cache includes a tag RAM; and
the controller is configured to select the first cache line to evict by walking the tag RAM.
3. The device of claim 1 , wherein the controller is configured to select the first cache line based on a first-in-first-out policy.
4. The device of claim 1 , wherein the controller is configured to select the first cache line based on a least recently used policy.
5. The device of claim 1 , wherein the controller is configured to select the first cache line based on a random selection policy.
6. The device of claim 1 , wherein:
the cache includes a drain buffer; and
the controller is configured to evict the first cache line by storing the packet in the drain buffer until an acknowledgment is received.
7. The device of claim 6 , wherein:
the cache is a first cache;
the device further comprises a second cache coupled to the processor;
the controller is configured to provide the packet to the second cache; and
the second cache is configured to provide the acknowledgment.
8. The device of claim 1 , wherein:
the cache memory is a victim cache memory; and
the set of line type entries each specify whether the respective line of the set of cache lines is associated with a write-miss entry or a victim cache entry.
9. The device of claim 1 , wherein the state is an idle state.
10. The device of claim 9 , wherein the controller is configured to select the first cache line to evict based on the processor interface being in the idle state for a number of clock cycles.
11. A device comprising:
an interface;
a cache memory that includes a set of cache lines that are each configurable to store either a first type of entry or a second type of entry, wherein:
the second type of entry is a write-miss entry; and
the set of cache lines includes a first cache line configurable to store a first write-miss entry; and
a cache controller coupled to the interface and to the cache memory and configured to:
detect a state of the interface; and
based on the state:
select the first cache line to evict; and
evict the first cache line by providing a packet based on the first write-miss entry stored in the first cache line.
12. The device of claim 11 , wherein:
the cache memory includes a set of line type entries that are each configured to store a respective value that specifies whether a respective line of the set of cache lines is configured to store the first type of entry or the second type of entry; and
the cache controller is configured to select the first cache line to evict based on the set of line type entries.
13. The device of claim 11 , wherein:
the device comprises a tag RAM; and
the cache controller is configured to select the first cache line to evict by walking the tag RAM.
14. The device of claim 11 , wherein the cache controller is configured to select the first cache line based on at least one of a first-in-first-out policy, a least recently used policy, or a random replacement policy.
15. The device of claim 11 , wherein:
the cache memory is a victim cache memory; and
the first type of entry is a victim cache entry.
16. The device of claim 11 , wherein the state is an idle state.
17. A method comprising:
storing a set of data in a cache line of a cache memory;
storing an indication of whether the set of data is associated with a write-miss entry;
detecting a state of a cache interface; and
based on the state:
selecting the set of data to evict based on the indication; and
evicting the set of data, wherein the evicting includes providing a packet based on the set of data.
18. The method of claim 17 , wherein the selecting of the set of data includes walking a set of tag RAM entries.
19. The method of claim 17 , wherein the selecting of the set of data includes applying at least one of a first-in-first-out policy, a least recently used policy, or a random replacement policy.
20. The method of claim 17 , wherein the indication specifies whether the set of data is associated with the write-miss entry or a victim cache entry.