Front side OHMIC contact formation for SiC device
Various embodiments of the present disclosure disclose improved silicon carbide (SiC) power devices and methods of fabrication of such devices. A SiC power device includes a semiconductor base material with a first side and a second side and a first metallic layer disposed on the first side of the semiconductor base material that forms ohmic contacts and Schottky contacts. The SiC power device may be fabricated by forming a first metallic layer on a first side of a semiconductor base material to form a Schottky contact, forming a second metallic layer over the first metallic layer to form a reflective barrier covering the Schottky contact, removing one or more portions of the second metallic layer to expose a first portion of the first metallic layer, and forming silicide portions on the first metallic layer to form ohmic contacts within the Schottky contact.
1 . A method comprising:
providing a semiconductor base material comprising a first side and a second side, wherein the semiconductor base material comprises a silicon carbide (SiC) material;
forming a first metallic layer on the first side of the semiconductor base material to form a Schottky contact;
forming a second metallic layer over the first metallic layer to form a reflective barrier layer covering the Schottky contact;
removing one or more portions of the second metallic layer to expose a first portion of the first metallic layer; and
forming, through a laser annealing process, one or more silicide portions on the first metallic layer to form one or more ohmic contacts within the Schottky contact.
2 . The method of claim 1 , wherein the first metallic layer forms the one or more ohmic contacts and the Schottky contact within a p+ region.
3 . The method of claim 1 further comprising, subsequent to forming the one or more silicide portions on the first metallic layer, forming a dielectric layer on the first side of the semiconductor base material, wherein the dielectric layer covers the semiconductor base material, the first metallic layer, and the second metallic layer.
4 . The method of claim 3 further comprising:
placing a dielectric layer mask over one or more peripheral dielectric portions of the dielectric layer;
etching an interior dielectric portion from the dielectric layer to expose the second metallic layer and the one or more silicide portions on the first metallic layer; and
removing the dielectric layer mask.
5 . The method of claim 4 further comprising:
forming a frontside metallic layer over the first side of the semiconductor base material, the dielectric layer, the first metallic layer, and the second metallic layer;
placing a frontside metallic layer mask over an interior portion of the frontside metallic layer;
etching a peripheral frontside metallic portion from the frontside metallic layer to expose the dielectric layer; and
removing the frontside metallic layer mask.
6 . The method of claim 5 further comprising:
forming a passivation layer over the dielectric layer and the frontside metallic layer;
placing a passivation layer mask over a peripheral portion of the passivation layer;
etching an interior passivation layer portion from the passivation layer to expose the frontside metallic layer; and
removing the passivation layer mask.
7 . The method of claim 1 , wherein removing the one or more portions of the second metallic layer comprises:
placing a patterned mask over the second metallic layer, wherein the patterned mask exposes the one or more portions of the second metallic layer;
etching the second metallic layer, through the patterned mask, to remove the one or more portions of the second metallic layer; and
removing the patterned mask.
8 . The method of claim 1 further comprising, subsequent to forming the one or more silicide portions on the first metallic layer, removing one or more peripheral portions of the first metallic layer and the second metallic layer to expose at least a portion of the semiconductor base material.
9 . The method of claim 8 wherein removing the one or more peripheral portions of the first metallic layer comprises:
placing an interior mask over the second metallic layer, wherein the interior mask exposes the one or more peripheral portions of the second metallic layer;
etching the second metallic layer and the first metallic layer, around the interior mask, to remove the one or more peripheral portions of the second metallic layer and the first metallic layer; and
removing the interior mask.
10 . The method of claim 1 wherein the semiconductor base material comprises one or more anode implants and the one or more silicide portions on the first metallic layer correspond to the one or more anode implants.
11 . The method of claim 10 further comprising forming the one or more anode implants within the first side of the semiconductor base material.
12 . The method of claim 1 , wherein the first side of the semiconductor base material comprises an epitaxial drift layer and the second side of the semiconductor base material comprises a doped SiC substrate.
13 . The method of claim 12 further comprising:
forming a backside ohmic contact on the second side of the semiconductor base material; and
forming a backside metallic layer over the backside ohmic contact.
14 . The method of claim 1 , wherein the first metallic layer comprises a nickel-based material.
15 . The method of claim 1 , wherein the second metallic layer comprises an aluminum-based material.