IP Library › Granted Patent US 12,557,676
Granted Patent B2
US 12,557,676 · App. 18/342,061 · Granted Feb 17, 2026

Array substrate, display module and display apparatus each having functional area with bending area

Inventors: Lei Mi (Hefei, CN); Yusheng Liu (Hefei, CN); Hongrui Li (Hefei, CN)
Assignee: Hefei Visionox Technology Co., Ltd.
H01L23/49838H01L23/49827
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Quick Facts
Patent No.
US 12,557,676
App. No.
18/342,061
Granted
Feb 17, 2026
Kind
B2
Abstract

An array substrate, a display module and a display apparatus and belongs to the field of display technology. The array substrate includes: first data lines located in the central area and extending along the first direction; second data lines located in the edge area and extending along the first direction; first connecting lines located between the central area and the functional area and extending along the first direction, the first connecting lines being electrically connected with the first data lines in a one-to-one correspondence; second connecting lines electrically connected with the second data lines in a one-to-one correspondence; and line-switching connecting units electrically connected with the second connecting lines and connecting ports, so that the second data lines are electrically connected, via the second connecting lines and the line-switching connecting units, with the connecting ports in an arrangement order of the second data lines.

Claims (50)

1 . An array substrate, comprising:

a display area comprising a central area and an edge area located on at least a side of the central area along a second direction;

a non-display area comprising a functional area spaced from the display area in a first direction;

a plurality of first data lines located in the central area and extending along the first direction, the plurality of first data lines being arranged at intervals along the second direction;

a plurality of second data lines located in the edge area and extending along the first direction, the plurality of second data lines being arranged at intervals along the second direction;

a plurality of first connecting lines located between the central area and the functional area and extending along the first direction, the first connecting lines being electrically connected with the first data lines in a one-to-one correspondence;

a plurality of second connecting lines electrically connected with the second data lines in a one-to-one correspondence, the second connecting line comprising a first connecting line segment and a second connecting line segment distributed successively, the second connecting line segment extending along the first direction between the central area and the functional area;

wherein the functional area comprises a bending area,

under a condition that a length of the bending area along the second direction is less than a length of the functional area along the second direction, the array substrate further comprises a plurality of third connecting lines, the third connecting lines are electrically connected with the second connecting line segments and the first connecting lines in a one-to-one correspondence, an area on the array substrate in which the plurality of third connecting lines are located forms a sector wiring area.

2 . The array substrate of claim 1 , wherein the plurality of first connecting line segments comprise a plurality of first connecting sub-line segments extending along the second direction and a plurality of second connecting sub-line segments extending along the first direction, the plurality of first connecting sub-line segments are electrically connected with the plurality of second connecting sub-line segments.

3 . The array substrate of claim 1 , wherein a part of at least one first connecting line segment extending along the first direction is located between adjacent two of the first data lines.

4 . The array substrate of claim 1 , wherein

the first connecting line segment is a bending line extending in the display area, and

the array substrate further comprises a plurality of line-switching connecting units configured to be electrically connected with the second connecting lines and connecting ports, so that the second data lines are electrically connected, via the second connecting lines and the line-switching connecting units, with the connecting ports arranged in an order corresponding to an arrangement order of the second data lines, the connecting ports being electrically connected with a driver integrated circuit chip.

5 . The array substrate of claim 4 , wherein the plurality of line-switching connecting units comprises:

line-switching connecting lines electrically connected with the second connecting lines in a one-to-one correspondence and electrically connected with the connecting ports in an order corresponding to the connected second connecting lines.

6 . The array substrate of claim 5 , wherein the line-switching connecting lines comprise a plurality of first line-switching connecting line segments extending along the second direction and a plurality of second line-switching connecting line segments extending along the first direction, the plurality of first line-switching connecting line segments are electrically connected with the second connecting lines and the plurality of second line-switching connecting line segments, the plurality of second line-switching connecting line segments are electrically connected with the connecting ports.

7 . The array substrate of claim 6 , wherein at least one of the plurality of first line-switching connecting line segments extends in a direction from the edge area to the central area and beyond the second connecting line connected with the first line-switching connecting line segment.

8 . The array substrate of claim 6 , wherein the plurality of first line-switching connecting line segments extend in a direction from the edge area to the central area and beyond the second connecting line nearest to a center of the central area.

9 . The array substrate of claim 1 , wherein the array substrate further comprises a plurality of fourth connecting lines located in the bending area and extending along the first direction, the fourth connecting lines are electrically connected with the third connecting lines in a one-to-one correspondence.

10 . The array substrate of claim 1 , further comprising:

compensation lines located between the connecting ports and the driver integrated circuit chip and extending along the first direction, the compensation lines being electrically connected with the first connecting lines.

11 . The array substrate of claim 1 , wherein the second connecting lines and the second data lines are arranged in a same layer.

12 . The array substrate of claim 1 , wherein the second connecting lines and the second data lines are arranged in different layers, and the second connecting lines are located in a target metal layer between a substrate and an active layer.

13 . The array substrate of claim 12 , wherein a metal layer comprising the second data lines is located between the active layer and an anode metal layer.

14 . The array substrate of claim 12 , wherein the second connecting lines and the second data line are electrically connected via through-holes.

15 . The array substrate of claim 1 , wherein the edge area comprises an area of the central area protruding relative to the functional area along the second direction.

16 . An array substrate, comprising:

a display area comprising a central area and an edge area located on at least a side of the central area along a second direction;

a non-display area comprising a functional area spaced from the display area in a first direction;

a plurality of first data lines located in the central area and extending along the first direction, the plurality of first data lines being arranged at intervals along the second direction;

a plurality of second data lines located in the edge area and extending along the first direction, the plurality of second data lines being arranged at intervals along the second direction;

a plurality of first connecting lines located between the central area and the functional area and extending along the first direction, the first connecting lines being electrically connected with the first data lines in a one-to-one correspondence;

a plurality of second connecting lines electrically connected with the second data lines in a one-to-one correspondence, the second connecting line comprising a first connecting line segment and a second connecting line segment distributed successively, the first connecting line segment being a bending line extending in the display area, the second connecting line segment extending along the first direction between the central area and the functional area; and

a plurality of line-switching connecting units configured to be electrically connected with the second connecting lines and connecting ports, so that the second data lines are electrically connected, via the second connecting lines and the line-switching connecting units, with the connecting ports arranged in an order corresponding to an arrangement order of the second data lines, the connecting ports being electrically connected with a driver integrated circuit chip;

wherein the functional area comprises a bending area,

under a condition that a length of the bending area along the second direction is equal to a length of the functional area along the second direction, the first connecting lines and the second connecting line segments extend into the bending area along the first direction.

17 . An array substrate, comprising:

a display area comprising a central area and an edge area located on at least a side of the central area along a second direction;

a non-display area comprising a functional area spaced from the display area in a first direction;

a plurality of first data lines located in the central area and extending along the first direction, the plurality of first data lines being arranged at intervals along the second direction;

a plurality of second data lines located in the edge area and extending along the first direction, the plurality of second data lines being arranged at intervals along the second direction;

a plurality of first connecting lines located between the central area and the functional area and extending along the first direction, the first connecting lines being electrically connected with the first data lines in a one-to-one correspondence;

a plurality of second connecting lines electrically connected with the second data lines in a one-to-one correspondence, the second connecting line comprising a first connecting line segment and a second connecting line segment distributed successively, the second connecting line segment extending along the first direction between the central area and the functional area;

wherein a metal layer comprising the second data lines is located between an active layer and an anode metal layer, and

the second connecting lines and the second data line are electrically connected via through-holes.

18 . The array substrate of claim 17 , wherein

the array substrate further comprises a plurality of line-switching connecting units configured to be electrically connected with the second connecting lines and connecting ports, so that the second data lines are electrically connected, via the second connecting lines and the line-switching connecting units, with the connecting ports arranged in an order corresponding to an arrangement order of the second data lines, the connecting ports being electrically connected with a driver integrated circuit chip;

the second connecting lines and the second data lines are arranged in different layers, and the second connecting lines are located in a target metal layer between a substrate and the active layer; and

the first connecting line segment is a bending line extending in the display area.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2023
From: MI, LEI; LIU, YUSHENG; LI, HONGRUI
To: HEFEI VISIONOX TECHNOLOGY CO., LTD.
Reel/Frame 064085/0618 →
Priority Claims (1)
CN 202110846778.4 · Jul 26, 2021 · national
Continuity (2)
Continuation PCTCN2022082185 · Mar 22, 2022
Related Publication 20230352391A1 · Nov 2, 2023
References Cited (36)
US 20140175436A1 · Yamazaki · 2014 [cited by examiner]
US 20140259602A1 · Thompson · 2014 [cited by applicant]
US 20180267657A1 · Shao et al. · 2018 [cited by applicant]
US 20190272790A1 · Chang et al. · 2019 [cited by applicant]
US 20210375173A1 · Wang · 2021 [cited by examiner]
US 20210408210A1 · Kang · 2021 [cited by examiner]
CN 104752442A · 2015 [cited by applicant]
CN 107154218A · 2017 [cited by applicant]
CN 107300793A · 2017 [cited by applicant]
CN 207008253U · 2018 [cited by applicant]
CN 207517694U · 2018 [cited by applicant]
CN 108447887A · 2018 [cited by applicant]
CN 109270759A · 2019 [cited by applicant]
CN 109494243A · 2019 [cited by applicant]
CN 109541865A · 2019 [cited by applicant]
CN 109637372A · 2019 [cited by applicant]
CN 109935169A · 2019 [cited by applicant]
CN 110286534A · 2019 [cited by applicant]
CN 110416254A · 2019 [cited by applicant]
CN 107861279 · 2020 [cited by applicant]
CN 111223436A · 2020 [cited by applicant]
CN 111930266A · 2020 [cited by applicant]
CN 112071209A · 2020 [cited by applicant]
CN 113539108A · 2021 [cited by applicant]
JP 2001118847A · 2001 [cited by applicant]
JP 2004253303A · 2004 [cited by applicant]
JP 2007163703A · 2007 [cited by applicant]
JP 2008287285A · 2008 [cited by applicant]
JP 2010002876A · 2010 [cited by applicant]
KR 1020150057323A · 2015 [cited by applicant]
KR 1020180030007A · 2018 [cited by applicant]
KR 1020180042504A · 2018 [cited by applicant]
KR 1020210074489A · 2021 [cited by applicant]
Office Action issued on Jul. 18, 2023, in corresponding Chinese Application No. 202110846778.4, 5 pages. [cited by applicant]
Office Action issued on Jan. 12, 2023, in corresponding Chinese Application No. 202110846778.4, 21 pages. [cited by applicant]
International Search Report issued on Jul. 19, 2022, in corresponding International Application No. PCT/CN2022/082185, 4 pages. [cited by applicant]