Fault protected signal splitter apparatus

1. A splitter board system comprising:

a microprocessor; and

a converter coupled with the microprocessor, the converter comprising analog-to-digital circuitry and digital-to-analog circuitry,

wherein the converter is configured to:

receive an analog input signal,

generate a first duplicated instance of the analog input signal,

generate a second duplicated instance of the analog input signal,

direct the first duplicated instance to an output port of the splitter board system for downstream processes,

convert the second duplicated instance of the analog input signal into a digital signal, and

output the digital signal to an external server device.

2. The splitter board system of claim 1 , wherein the converter is further configured to:

convert the first duplicated instance to a second digital signal, and

direct the second digital signal to the microprocessor prior to output via the output port.

3. The splitter board system of claim 2 , wherein the microprocessor applies calibration factors to the second digital signal and returns the second digital signal to the converter after the calibration factors are applied.

4. The splitter board system of claim 3 , wherein the converter is further configured to:

convert the second digital signal back to an analog signal.

5. The splitter board system of claim 1 , further comprising:

a bypass coupled with the converter and the microprocessor, the bypass configurable between a first state and a second state.

6. The splitter board system of claim 5 , wherein, in the first state, the bypass directs the analog input signal to the converter.

7. The splitter board system of claim 5 , wherein, in the second state, the bypass directs a second input analog signal towards the output port, bypassing the converter.

8. A splitter board system comprising:

a converter;

a bypass coupled to the converter, the bypass configurable between a first state and a second state; and

a microprocessor coupled with the converter and the bypass, the microprocessor configured to switch the bypass between the first state and the second state,

wherein, in the first state, the bypass directs a fault protected input signal to the converter, wherein the converter splits the fault protected input signal into a first portion and a second portion, wherein the converter directs the first portion of the fault protected input signal to an output port of the splitter board system for downstream processes and outputs the second portion to an external server device, and

wherein, in the second state, the bypass causes the fault protected input signal to bypass the converter and directs the fault protected input signal to the output port of the splitter board system for the downstream processes.

9. The splitter board system of claim 8 , wherein the converter directs the first portion of the fault protected input signal to the microprocessor prior to output.

10. The splitter board system of claim 9 , wherein the microprocessor applies calibration factors to the second portion of the fault protected input signal and returns the second portion of the fault protected input signal to the converter after the calibration factors are applied.

11. The splitter board system of claim 10 , wherein the converter is further configured to:

convert the second portion of the fault protected input signal back to an analog signal.

12. The splitter board system of claim 8 , wherein the converter comprising:

a fault detection module configured to detect when at least one component of the splitter board system fails.

13. The splitter board system of claim 12 , wherein the microprocessor is configured to read the fault detection module to determine when the at least one component of the splitter board system fails.

14. The splitter board system of claim 12 , wherein the converter is configured to convert the fault protected input signal from a first signal type to a second signal type, wherein the first signal type is selected from a first group comprising a digital signal and an analog signal, and wherein the second signal type is selected from a second group comprising a digital signal and an analog signal.

15. A method comprising:

receiving, by a converter of a signal splitter board, an analog input signal;

generating, by the converter, a first duplicated instance of the analog input signal and a second duplicated instance of the analog input signal;

directing, by the converter, the first duplicated instance to an output port of the signal splitter board for downstream processes;

converting, by the converter, the second duplicated instance of the analog input signal into a digital signal, and

outputting, by the converter, the digital signal to an external server device.

16. The method of claim 15 , further comprising:

converting, by the converter, the first duplicated instance to a second digital signal, and

directing, by the converter, the second digital signal to a microprocessor of the signal splitter board prior to output via the output port.

17. The method of claim 16 , further comprising:

applying, by the microprocessor, calibration factors to the second digital signal; and

returning, by the microprocessor, the second digital signal to the converter after the calibration factors are applied.

18. The method of claim 17 , further comprising:

converting, by the converter, the second digital signal back to an analog signal.

19. The method of claim 15 , wherein the converter comprises a fault detection module.

20. The method of claim 19 , further comprising:

determining, by the fault detection module, that no component of the signal splitter board failed.