Granted Patent B2

US 12,360,840 · App. 18/346,753 · Granted Jul 15, 2025

Inventors: Kai Huang (Zhejiang, CN); Siheng Chen (Zhejiang, CN); Xiaowen Jiang (Zhejiang, CN); Xiaoxu Zhang (Zhejiang, CN); Zhili Liu (Zhejiang, CN); Wenyuan Xu (Zhejiang, CN); Yonggang Peng (Zhejiang, CN)

Assignee: ZHEJIANG UNIVERSITY

G06F11/0793G06F11/0724

Abstract

Claims (16)

1. A fault-tolerant system comprising:

multi-core central processing units (CPUs) capable of being dynamically configured, wherein the multi-core CPUs are three reconfigurable CPUs,

wherein the fault-tolerant system with multi-core CPUs is statically configured to be in a normal fault-tolerant mode, a reliable fault-tolerant mode or a performance mode by configuration of the three CPUs and is switched between the normal fault-tolerant mode, the reliable fault-tolerant mode and the performance mode according to a mode switching command of a mode switching register, and, the three CPUs are correspondingly configured according to which modes the three CPUs are switched;

wherein the fault-tolerant system being switched between the performance mode and the normal fault-tolerant mode is specifically as follows:

setting a starting time of the system as T 0 , the three CPUs comprising CPU 0 , CPU 1 and CPU 2 , CPU 0 and CPU 1 independently running a code;

performing checkpoint saving by the three CPUs on a respective operating state at time T 1 of each of the three CPUs, a saving state of CPU 0 being checkpoint A 1 , and a saving state of CPU 1 being checkpoint B 1 , which are used for subsequent state switching or recovery; wherein between T 1 and T 2 , CPU 0 and CPU 1 receive a dual modular redundancy mode switching command, but the command does not take effect at this time;

at time T 2 , executing operations of checkpoints A 2 and A 3 by CPU 0 , and executing operations of checkpoints B 2 and B 3 by CPU 1 ;

the mode switching command taking effect at time T 3 , an input signal of CPU 1 being switched into input of CPU 0 , output being generated by CPU 0 for a fault monitoring pair, CPU 0 and CPU 1 being reset at a same time, the checkpoint A 1 state is loaded, and after resetting, CPU 0 and CPU 1 retrieving an address of a next instruction saved in the checkpoint A 1 state from a 0x0 address to complete mode switching and run in the normal fault-tolerant mode; and

when the fault-tolerant system with multi-core CPUs is switched to the normal fault-tolerant mode, the three CPUs being set as a combination of a dual modular lockstep architecture and single-core independent operation,

when the fault-tolerant system with multi-core CPUs is switched to the reliable fault-tolerant mode, the three CPUs being set to be in triple modular redundancy, and

when the fault-tolerant system with multi-core CPUs is switched to the performance mode, the three CPUs being set to be in triple-core independent operation.

2. The fault-tolerant system with multi-core CPUs capable of being dynamically configured according to claim 1 , wherein a dual-core lockstep fault-tolerant method is employed in the normal fault-tolerant mode, the three CPUs are set as a combination of a dual modular lockstep architecture and single-core independent operation, based on the checkpoint method, the two CPUs of the dual modular lockstep architecture run in a master-slave mode to form a self-monitoring pair, a slave CPU receives the same input data stream as a master CPU and performs the same operation, the slave CPU serves as a checker for checking correctness of an output data stream of the master CPU, performs outputting after performing a comparison in lockstep modules of the master and slave CPUs, and stores a correct state obtained by checking in real time, and resetting and state loading are performed on the master CPU and the slave CPU when a fault occurs.

3. The fault-tolerant system with multi-core CPUs capable of being dynamically configured according to claim 1 , wherein the reliable fault-tolerant mode is a triple modular redundancy mode, the three CPUs when the triple modular redundancy mode have a same master CPU input data stream, the input data stream is subjected to parity check coding for fault tolerance, and 1 bit data stream output is given to an external output signal of the master CPU after triple modular majority voting.

4. The fault-tolerant system with multi-core CPUs capable of being dynamically configured according to claim 3 , wherein in the triple modular redundancy mode, when it is detected that an output of one of the three CPUs is inconsistent with outputs of the other two CPUs, a fault count of a current faulty CPU is recorded, a fault counter is incremented after recording a fault, when the counter counts to a configurable value, it is speculated that the CPU is in an out-of-step operation with the other two CPUs, and re-synchronization is completed by resetting and reloading of a correct state.

5. The fault-tolerant system with multi-core CPUs capable of being dynamically configured according to claim 1 , wherein switching between the performance mode and the reliable fault-tolerant mode is specifically as follows: a starting time of the system being T 0 , the three CPUs are CPU 0 , CPU 1 and CPU 2 respectively, which independently run a code, checkpoint saving is performed on the respective operating state of each of the three CPUs at time T 1 , a saving state of CPU 0 is checkpoint A 1 , a saving state of CPU 1 is checkpoint B 1 , and a saving state of CPU 2 is checkpoint C 1 , which are used for subsequent state switching or recovery; wherein between T 1 and T 2 , the three CPUs receive a reliable fault-tolerant mode switching command, but the command does not take effect at this time, at time T 2 , CPU 0 executes operations of checkpoints A 2 and A 3 , CPU 1 executes operations of checkpoints B 2 and B 3 , and CPU 2 executes operations of checkpoints C 2 and C 3 ; and the mode switching command takes effect at time T 3 , input signals of CPU 1 and CPU 2 are switched into input of CPU 0 , output of the three CPUs is output after majority voting, the three CPUs are reset at the same time, the checkpoint A 1 state saved by the master core CPU 0 before the mode switching command is initiated is loaded, and after resetting, CPU 0 , CPU 1 and CPU 2 retrieve an address of a next instruction saved in the checkpoint A 1 state from a 0x0 address to complete mode switching and run in the reliable fault-tolerant mode.

6. A method for the fault-tolerant system with multi-core CPUs capable of being dynamically configured according to claim 1 , wherein switching between the normal fault-tolerant mode and the reliable fault-tolerant mode is specifically as follows: a starting time of the system being T 0 , the three CPUs are CPU 0 , CPU 1 and CPU 2 respectively, CPU 0 and CPU 1 run a code in a dual modular redundancy mode, CPU 2 independently runs a code, checkpoint saving is performed on the respective operating state at time T 1 , a saving state of the dual modular redundancy mode is checkpoint A 1 , and a saving state of CPU 2 is checkpoint C 1 , which are used for subsequent state switching or recovery; between T 1 and T 2 , the three CPUs receive a triple modular redundancy reliable fault-tolerant mode switching command, but the command does not take effect at this time, at time T 2 , operations of checkpoints A 2 and A 3 are executed in the dual modular redundancy mode, and CPU 2 executes operations of checkpoints C 2 and C 3 ; and the mode switching command takes effect at time T 3 , an input signal of CPU 2 is switched into input of the dual modular redundancy mode, output of the three CPUs is output after majority voting, the three CPUs are reset at the same time, the checkpoint A 1 state saved by the dual modular redundancy mode before the mode switching command is initiated is loaded, and after resetting, CPU 0 , CPU 1 and CPU 2 retrieve an address of a next instruction saved in the checkpoint A 1 state from a 0x0 address to complete mode switching and run in the reliable fault-tolerant mode.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (14)