Semiconductor device and method of manufacturing the same
A semiconductor device includes a semiconductor substrate, a first insulating film formed on an upper surface of the semiconductor substrate in an outer peripheral region so as to surround a cell region in plan view, and a resistive element formed on the first insulating film so as to surround the cell region in plan view. A second insulating film having a thickness thinner than that of the first insulating film is formed on the upper surface of the semiconductor substrate in the outer peripheral region. A dummy pattern is formed from a portion over the second insulating film to a portion over the first insulating film so as to cover a step occurring between the second insulating film and the first insulating film.
1 . A semiconductor device including a cell region in which a MOSFET is formed and an outer peripheral region surrounding the cell region in plan view, comprising:
a semiconductor substrate of a first conductivity type, the semiconductor substrate having an upper surface and a lower surface;
a first insulating film formed on the upper surface of the semiconductor substrate in the outer peripheral region so as to surround the cell region in plan view; and
a resistive element formed on the first insulating film so as to surround the cell region in plan view,
wherein a second insulation film having a thickness thinner than a thickness of the first insulation film is formed on the upper surface of the semiconductor substrate in the outer peripheral region, and
wherein a first dummy pattern is formed from a portion over the second insulating film to a portion over the first insulating film so as to cover a step occurring between the second insulating film and the first insulating film.
2 . The semiconductor device according to claim 1 , wherein the first dummy pattern is not electrically connected with each of the MOSFET and the resistive element.
3 . The semiconductor device according to claim 1 , wherein a second dummy pattern is formed on a side surface of the first dummy pattern, which is formed at a position higher than the first insulating film, via a third insulating film.
4 . The semiconductor device according to claim 3 , wherein the first dummy pattern and the second dummy pattern are not electrically connected with each of the MOSFET and the resistive element.
5 . The semiconductor device according to claim 1 , wherein a thickness of the first dummy pattern is thinner than a thickness of the first insulating film.
6 . The semiconductor device according to claim 1 , wherein the resistive element includes:
a resistance portion formed in a spiral shape;
a first contact portion integrated with the resistance portion and located at an inner side of the resistance portion; and
a second contact portion integrated with the resistance portion and located at an outer side of the resistance portion.
7 . The semiconductor device according to claim 6 ,
wherein the MOSFET includes:
a gate insulating film formed on the upper surface of the semiconductor substrate in the cell region;
a gate electrode formed on the gate insulating film;
a body region of a second conductivity type opposite the first conductivity type, the body region being formed in the semiconductor substrate in the cell region at a portion located closer to the upper surface than the lower surface; and
a source region of the first conductivity type,
the source region being formed in the body region,
wherein the gate insulating film is made of an insulating film which is the same as the second insulating film, and
wherein the gate electrode is made of a conductive film which is the same as the first dummy pattern, and which is different from the resistive element.
8 . The semiconductor device according to claim 7 , further comprising:
an interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the MOSFET in the cell region and to cover the resistive element, the first dummy pattern and the first insulating film in the outer peripheral region;
a first hole formed in the interlayer insulating film and reaching the first contact portion;
a second hole formed in the interlayer insulating film and reaching the second contact portion;
a third hole formed in the interlayer insulating film and reaching the semiconductor substrate in the outer peripheral region;
a fourth hole formed in the interlayer insulating film and reaching the source region;
a fifth hole formed in the interlayer insulating film and reaching the gate electrode;
a source electrode formed on the interlayer insulating film;
a gate wiring formed on the interlayer insulating film and surrounding the source electrode in plan view;
a source wiring formed on the interlayer insulating film, surrounding the gate wiring in plan view, and electrically connected with the source electrode;
a drain wiring formed on the interlayer insulating film and surrounding the source wiring in plan view; and
a drain electrode formed on the lower surface of the semiconductor substrate,
wherein the source wiring is embedded in the first hole, and electrically connected with the first contact portion,
wherein the drain wiring is embedded in each of the second hole and the third hole, and electrically connected with each of the second contact portion and the semiconductor substrate,
wherein the source electrode is embedded in the fourth hole, and electrically connected with the source region, and
wherein the gate wiring is embedded in the fifth hole, and electrically connected with the gate electrode.
9 . The semiconductor device according to claim 1 ,
wherein an impurity of the first conductivity type is introduced into the first dummy pattern, and
wherein an impurity of a second conductivity type different from the first conductivity type is introduced into the resistive element.