Semiconductor device and method of manufacturing the same
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
1 . A semiconductor device comprising:
a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a first trench and a second trench formed on the semiconductor substrate;
a first trench emitter formed in the first trench via a first gate insulating film;
a first trench gate formed in the second trench via a second gate insulating film;
a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the first trench emitter and the first trench gate; and
a crystal defect region including crystal defects selectively formed at a position near the first main surface in the floating region, wherein
in cross-sectional view, the floating region is formed to cover a bottom surface of the first trench and a bottom surface of the second trench, and
in plan view and cross-sectional view, the crystal defect region separates apart from the first trench and the second trench.
2 . The semiconductor device according to claim 1 , wherein
the crystal defect region is located in the floating region and the crystal defect region does not contact with the first trench and the second trench.
3 . The semiconductor device according to claim 1 , further comprising:
a third trench formed beside the first trench and on the semiconductor substrate in a direction opposite to a direction in which the second trench is formed in plan view;
a second trench emitter formed in the third trench via a third gate insulating film;
a first base region of the first conductivity type formed in the semiconductor substrate sandwiched between the first trench emitter and the second trench emitter;
an interlayer insulating film formed on the first main surface such that the interlayer insulating film covers the first trench emitter, the second trench emitter, the first trench gate, the first base region and the crystal defect region;
a first contact member formed in the interlayer insulating film such that the first contact member penetrates through the interlayer insulating film and reaches the first main surface; and
an emitter electrode formed on the interlayer insulating film, wherein
the first contact member contacts with the first trench emitter, the second trench emitter, the first base region and the emitter electrode.
4 . The semiconductor device according to claim 3 , further comprising:
a first contact hole penetrated through the interlayer insulating film and reached the first main surface; and
in the first contact hole, a recess formed from the first main surface toward the second main surface such that the recess traversed the first trench emitter, the first base region and the second trench emitter in plan view, wherein
the first contact member is formed as to fill in the first contact hole and the recess.
5 . The semiconductor device according to claim 3 , further comprising:
a fourth trench formed beside the second trench and on the semiconductor substrate in a direction opposite to a direction in which the first trench is formed in plan view;
a second trench gate formed in the fourth trench via a fourth gate insulating film;
a second base region of the first conductivity type formed in the semiconductor substrate sandwiched between the first trench gate and the second trench gate;
an emitter region of a second conductivity type opposite to the first conductivity type formed in the first main surface and on the second base region;
a second contact member formed in the interlayer insulating film such that the second contact member penetrates through the interlayer insulating film and reaches the first main surface;
wherein
the second contact member contacts with the emitter region, the second base region and the emitter electrode.
6 . The semiconductor device according to claim 5 , further comprising:
a gate electrode formed on the first main surface and electrically connected to the first trench gate and the second trench gate; and
a collector electrode formed on the second main surface, wherein
the emitter electrode electrically connects with the first trench emitter, the second trench emitter, the first base region, the second base region and the emitter region, and
the emitter electrode, the gate electrode and the collector electrode configure an IGBT.
7 . The semiconductor device according to claim 6 , wherein
the crystal defect region is formed in the floating region where is not depleted in an off-state of the IGBT.
8 . The semiconductor device according to claim 1 , wherein
a high crystal defect density portion of the crystal defects in the crystal defect region is located near the first main surface.
9 . The semiconductor device according to claim 1 , wherein
a maximum density of the crystal defects is 1×103/cm2 or less.
10 . The semiconductor device according to claim 1 , wherein
the first trench emitter, and the first trench gate are extended in a first direction and located side by side in a second direction intersecting the first direction.