Securing conditional speculative instruction execution
View Patent ↗A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.
1 . A device, comprising:
a memory; and
a processor coupled to the memory and configured to determine, based on an identity of an object associated with a subsequent instruction to be executed following a branch instruction, whether to speculatively execute the subsequent instruction.
2 . The device of claim 1 , wherein the processor is configured to determine, in response to the subsequent instruction configured to be executed following the branch instruction, whether to execute the subsequent instruction.
3 . The device of claim 1 , wherein the processor is configured to determine whether to execute the subsequent instruction during speculative instruction execution.
4 . The device of claim 3 , wherein the processor is a microprocessor.
5 . The device of claim 4 , wherein the microprocessor includes:
a register configured to store a memory address configured to identify the object.
6 . The device of claim 5 , wherein the microprocessor further includes:
an execution unit configured to execute the branch instruction using the memory address in the register.
7 . The device of claim 6 , wherein the memory address is further configured to identify an offset of the subsequent instruction in the object.
8 . The device of claim 4 , wherein the memory is configured to store the object containing the subsequent instruction.
9 . The device of claim 1 , wherein the processor is configured to whether to execute the subsequent instruction based on whether the object is different from an object associated with the branch instruction.
10 . The device of claim 1 , wherein the processor is configured to whether to execute the subsequent instruction based on whether the object is a kernel of an operating system.
11 . The device of claim 1 , wherein the processor is configured to prevent execution of the subsequent instruction in response to a determination that the object is a kernel of an operating system.
12 . A method, comprising:
storing, in a memory, an object having a subsequent instruction to be executed following a branch instruction; and
determining, by a processor coupled to the memory and based on an identity of the object, whether to speculatively execute the subsequent instruction.
13 . The method of claim 12 , wherein the determining is in response to the subsequent instruction configured to be executed following the branch instruction.
14 . The method of claim 12 , wherein the determining is during speculative instruction execution.
15 . The method of claim 14 , further comprising:
storing, in a register of the processor, a memory address configured to identify the object; and
executing the branch instruction using the memory address stored in the register.
16 . The method of claim 15 , wherein the memory address is further configured to identify an offset of the subsequent instruction in the object.
17 . The method of claim 13 , wherein the determining is based on whether the object is different from an object associated with the branch instruction.
18 . The method of claim 12 , further comprising:
preventing execution of the subsequent instruction in response to a determination that the object is a kernel of an operating system.
19 . A microprocessor, comprising:
a register configured to store a memory address configured to identify an object;
an execution unit configured to execute a first instruction using the memory address in the register;
wherein the microprocessor is configured to determine, based on an identity of the object, whether to execute a second instruction in the object, during speculative instruction execution.
20 . The microprocessor of claim 19 , wherein the memory address is configured to identify an offset of the second instruction in the object; and the microprocessor is further configured to determine whether to execute the second instruction during speculative instruction execution.